|Company||Motorola Semiconductor Products|
|Datasheet||Download 68HC912D60MSE4 datasheet
This mask-set errata provides information pertaining to the following 68HC912D60 MCU mask set devices: 4F73K, available from January 1999.Some items do not report bugs but only contain customer information.
The mask set is identified by a four-character code consisting of a letter, two numerical digits, and a letter, for example F74B. Slight variations to the mask set identification code may result in an optional numerical digit preceding the standard four-character code, for example 0F74B.
Device markings indicate the week of manufacture and the mask set used. The data is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. The date code "9115" would indicate the 15th week of the year 1991.
Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC, or ZC prefix denotes special/custom device. An XC prefix denotes device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC prefix.
When contacting a Motorola representative for assistance, please have the MCU device mask set and date code information available.Specifications and information herein are subject to change without notice.
If the (VRH-VRL)/2 internal reference is used (perhaps for system diagnostics), expected pass result may or $81.
This is primarily an issue only for developers of BDM interface equipment (BDM pods). The BDM logic was changed to allow switching between XTAL/2 and a possibly faster bus rate clock. If you set the CLKSW bit (faster bus rate clock) in the BDM STATUS register (with a WRITE_BD_BYTE @ FF01 command, and then later send a GO, TRACE1, or TAG_GO command (or encounter a $00 opcode with ENBDM=0), the CLKSW bit is cleared by BDM firmware such that the BDM speed switches back to the default (XTAL/2) rate.
When communicating at the bus rate (CLKSW=1), issue a new WRITE_BD_BYTE command (at the XTAL/2 rate) to set the CLKSW bit in BDM_STATUS after any GO, TRACE1, or TAG_GO command or if BDM communications fail unexpectedly.BDM: FAILURE TO RELEASE ADDRESS BUS AFTER MEMORY ACCESS AR538
When the BDM module is using XTAL/2 as its reference clock and the PLL is providing the clock for the CPU buses, a BDM logic circuit can fail to release control of the address bus after completing a memory access. When the next BDM serial command is completed, the BDM gives up control of the address bus, but by this time the CPU is already lost. This often results in the CPU eventually reaching a $00 opcode and getting into active BDM mode.
The error can be avoided if the BDM operates from the same clock source as the bus. Everything works after reset because both the BDM and the bus use XTAL/2 as the clock source. If the CLKSW bit is changed to one before engaging the PLL, the system also works (although the host must change communication speed to match the bus frequency changes). In some systems the PLL is turned on and off and the bus frequency can be changed at random intervals and there is no practical way for a host to track these changes without access to the E-clock frequency. In these systems there is no workaround.
When the BDM module is using synchronized (CLKSW=0) as its reference clock and the PLL is providing the clock for the CPU bus (BCSP=1), data cannot be read back correctly through the BDM. The chance of reading wrong data increases when the bus frequency increases (with different PLL prescaler). All data read will not be correct when the Bus frequency is near four times the XTAL frequency. READ_W will return the requested address as data. READ_B will return the upper and lower byte of address if the requested address is even and odd respectively. Write through BDM is normal.
No customer workaround is available for this clock selection. However, CLKSW=0, BCSP=0 (Supported by all bdm i/f software) and CLKSW=1, BCSP=1 (support is unknown) combination are still ok.
It is possible to lose BDM communication when executing long instructions, 11 cycles or more (IDIV, FDIV, EMACS, EDIVS, IDIVS), if the PLL is being used as the SYSCLK source.
Do not use the PLL as SYSCLK source when using the BDM interface to debug code that uses instructions taking 11 cycles, or insert a breakpoint before such an instruction and single step over it before continuing code execution.BKP: ADDRESS AND DATA REGISTERS RESET ONLY ON POR
Breakpoint Address and Data registers are properly reset only upon Power on Reset.
To ensure BRKAH, BRKAL, BRKDH and BRKDL registers have the correct default values, always clear each immediately after reset.CGM: CPU STOPS GOING INTO WAIT BEFORE STRETCHED CYCLE IS FINISHED AR475
When the device exits WAIT mode, it does not return to the correct location within the routine if the stack is positioned in external memory and if the stretch bits have been enabled to lengthen the clock.
To overcome this problem, locate the stack in internal RAM resources and/or clear the stretch bits to prevent clock stretching.
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