Details, datasheet, quote on part number: 68HC912DA128MSE4
Part68HC912DA128MSE4
Category
Description
CompanyMotorola Semiconductor Products
DatasheetDownload 68HC912DA128MSE4 datasheet
  

 

Features, Applications

This errata provides information applicable to the following MC68HC912DA128 MCU mask set devices: 0K50E

The mask set is identified by a four-character code consisting of a letter, two numerical digits, and a letter, for example F74B. Slight variations to the mask set identification code may result in an optional numerical digit preceding the standard four-character code, for example 0F74B.

Device markings indicate the week of manufacture and the mask set used. The data is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. The date code "9115" would indicate the 15th week of the year 1991.

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC, or ZC prefix denotes special/custom device. An XC prefix denotes device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC prefix.

When contacting a Motorola representative for assistance, please have the MCU device mask set and date code information available.

Specifications and information herein are subject to change without notice.

The variation of operational parameters within a given crystal part number may include a distribution of parts that present impedance conditions at start-up that will not function with the current design of the CGM. While typical parts may function correctly, problems may be seen in actual production runs.

Quartz crystal operation should be restricted to maximum 8MHz. 1. Use 8MHz (or slower) oscillator and generate higher bus frequencies using the PLL module. 2. Use alternative ceramic resonator. 3. Where mimimal clock jitter is critical, use external 'brick' quartz oscillator module.

INT: WAIT CANNOT BE EXITED IF XIRQ/IRQ LEVEL DEASSERTION OCCURS WITHIN PARTICULAR WINDOW OF TIME AR601

The device can get trapped in WAIT mode if, on exiting the WAIT instruction, the deassertion timing of the XIRQ or level-sensitive IRQ occurs within a particular timeframe. Only reset will allow recovery. Noise/bounce on the pins could also cause this problem.

1. Use edge-triggered IRQ (IRQE=1) instead of XIRQ or level-triggered IRQ. 2. Use RTI , timer interrupts, KWU or other interrupts (except level-sensitive IRQ or XIRQ) to exit WAIT. If using RTI, it must be enabled in WAIT (RSWAI=0) and the COP must be disabled (CME=0). 3. Assert XIRQ or level-sensitive IRQ until the interrupt subroutine is entered. 4. Add de-bouncing logic to prevent inadvertent highs when exiting WAIT.

If the (VRHVRL)/2 internal reference is used (perhaps for system diagnostics), expected pass result may or $81.

When the BDM module is using synchronized (CLKSW=0) as its reference clock and the PLL is providing the clock for the CPU bus (BCSP=1), data cannot be read back correctly through the BDM. The chance of reading wrong data increases when the bus frequency increases (with different PLL prescaler). All data read will not be correct when the Bus frequency is near four times the XTAL frequency. READ_W will return the requested address as data. READ_B will return the upper and lower byte of address if the requested address is even and odd respectively. Write through BDM is normal.

No customer workaround is available for this clock selection. However, CLKSW=0, BCSP=0 (Supported by all bdm i/f software) and CLKSW=1, BCSP=1 (support is unknown) combination are still ok.

STOP mode cannot be exited using interrupts when DLY=1 depending on where the Real-Time-Interrupt (RTI) counter is when the STOP instruction is executed. The RTI counter is free-running during normal operation and is only reset at the beginning of Reset, during Power-on-Reset, and after entry into STOP. The free-running counter will generate a one cycle pulse every 4096 cycles. If that pulse occurs at the exact same time that the stop signal from the CPU is asserted then the OSC is stopped but the internal stop signal will remain low. In this state the OSC is shut off until RESET.

1. If you are not using the Real Time Interrupt function you can wait for a RTI flag before entering into STOP to guarantee the counter in a safe state. When executing the following code all interrupt sources except for those used to exit STOP mode must be masked to prevent a loss of synchronization. A loss of synchronization can occur if an interrupt is processed between the setting of the RTIF and the execution of the STOP instruction. Also, you must enable the RTI counter in the initialization code, set to the fastest RTI time-out period, and the RTIE bit should NOT be set.

BRCLRRTIFLG,#RTIF,RTIFClr; RTIF flag is already clear LDAB#RTIF; if it's set, clear the flag. STABRTIFLG RTIFClr:BRCLRRTIFLG,#RTIF,*; wait until the RTIFLG is set. NOP STOP ; enter stop mode


 

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