Details, datasheet, quote on part number: 68HC912DG128MSE3
Part68HC912DG128MSE3
Category
Description
CompanyMotorola Semiconductor Products
DatasheetDownload 68HC912DG128MSE3 datasheet
  

 

Features, Applications

This errata provides information applicable to the following MC68HC912DG128 MCU mask set devices: 5H55W.A

The mask set is identified by a four-character code consisting of a letter, two numerical digits, and a letter, for example F74B. Slight variations to the mask set identification code may result in an optional numerical digit preceding the standard four-character code, for example 0F74B.

Device markings indicate the week of manufacture and the mask set used. The data is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. The date code "9115" would indicate the 15th week of the year 1991.

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC, or ZC prefix denotes special/custom device. An XC prefix denotes device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC prefix.

When contacting a Motorola representative for assistance, please have the MCU device mask set and date code information available.

Specifications and information herein are subject to change without notice.

If the (VRHVRL)/2 internal reference is used (perhaps for system diagnostics), expected pass result may or $81.

BDM: FAILURE TO RELEASE ADDRESS BUS AFTER MEMORY ACCESS AR538

When the BDM module is using XTAL/2 as its reference clock and the PLL is providing the clock for the CPU buses, a BDM logic circuit can fail to release control of the address bus after completing a memory access. When the next BDM serial command is completed, the BDM gives up control of the address bus, but by this time the CPU is already lost. This often results in the CPU eventually reaching a $00 opcode and getting into active BDM mode.

The error can be avoided if the BDM operates from the same clock source as the bus. Everything works after reset because both the BDM and the bus use XTAL/2 as the clock source. If the CLKSW bit is changed to one before engaging the PLL, the system also works (although the host must change communication speed to match the bus frequency changes). In some systems the PLL is turned on and off and the bus frequency can be changed at random intervals and there is no practical way for a host to track these changes without access to the E-clock frequency. In these systems there is no workaround.

When the BDM module is using synchronized (CLKSW=0) as its reference clock and the PLL is providing the clock for the CPU bus (BCSP=1), data cannot be read back correctly through the BDM. The chance of reading wrong data increases when the bus frequency increases (with different PLL prescaler). All data read will not be correct when the Bus frequency is near four times the XTAL frequency. READ_W will return the requested address as data. READ_B will return the upper and lower byte of address if the requested address is even and odd respectively. Write through BDM is normal.

No customer workaround is available for this clock selection. However, CLKSW=0, BCSP=0 (Supported by all bdm i/f software) and CLKSW=1, BCSP=1 (support is unknown) combination are still ok.

STOP mode cannot be exited using interrupts when DLY=1 depending on where the Real-Time-Interrupt (RTI) counter is when the STOP instruction is executed. The RTI counter is free-running during normal operation and is only reset at the beginning of Reset, during Power-on-Reset, and after entry into STOP. The free-running counter will generate a one cycle pulse every 4096 cycles. If that pulse occurs at the exact same time that the stop signal from the CPU is asserted then the OSC is stopped but the internal stop signal will remain low. In this state the OSC is shut off until RESET.

1. If you are not using the Real Time Interrupt function you can wait for a RTI flag before entering into STOP to guarantee the counter in a safe state. When executing the following code all interrupt sources except for those used to exit STOP mode must be masked to prevent a loss of synchronization. A loss of synchronization can occur if an interrupt is processed between the setting of the RTIF and the execution of the STOP instruction. Also, you must enable the RTI counter in the initialization code, set to the fastest RTI time-out period, and the RTIE bit should NOT be set.

BRCLRRTIFLG,#RTIF,RTIFClr; RTIF flag is already clear LDAB#RTIF; if it's set, clear the flag. STABRTIFLG RTIFClr:BRCLRRTIFLG,#RTIF,*; wait until the RTIFLG is set. NOP STOP ; enter stop mode

2. If you are driving a clock in (not using the OSC) then you could set DLY=0. 3. Pseudo-STOP and DLY=0 could be used. The oscillator will be kept alive during STOP at the expense of power consumption but no recovery delay is needed. Set the PSTP bit and clear DLY bit prior to going to STOP. 4. Limp Home and DLY=0 could be used. The part comes out of STOP in limp home mode while the crystal recovers. If a known frequency is not a requirement, this workaround avoids having the crystal alive in STOP mode. Clear the NOLHM and DLY bits prior to going to STOP.


 

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