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Part: DSP56009DS
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Company: Motorola Semiconductor Products
Datasheet: Download DSP56009DS datasheet File size : 331 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56009/D, Rev. 1
DSP56009
SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the SymphonyTM family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, Dolby AC-3 Surround, MPEG1 Layer 2, and Digital Theater Sound (DTS) processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, DVD applications, and automotive sound systems with such userdeveloped features as digital equalization and sound field processing. The DSP56009 is an MPUstyle general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core, program and data memories, various peripherals optimized for audio, and support circuitry. As illustrated in Figure 1, the DSP56000 core family compatible DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCETM) port. The DSP56009 has more on-chip memory than the DSP56004 or DSP56007.
4
General Purpose Input/ Output
9
Serial Audio Interface (SAI)
5
Serial Host Interface (SHI)
29
External Memory Interface (EMI)
16-Bit Bus 24-Bit Bus
Program Memory*
X Data Memory*
Y Data Memory*
24-Bit DSP56000 Core
Internal Data Bus Switch
Address Generation Unit
PAB XAB YAB
GDB PDB XDB YDB
OnCETM Port Clock Gen. Interrupt Control
PLL
Program Program Address Decode Generator Controller Program Control Unit
Data ALU 24 × 24 + 56 56-Bit MAC Two 56-Bit Accumulators
3
4
4
IRQA, IRQB, NMI, RESET
* Refer to Table 1 for memory configurations.
AA0248
Figure 1 DSP56009 Block Diagram
©1996, 1997 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
DSP56009/D, Rev. 1
MOTOROLA
DSP56009 Features
FEATURES Digital Signal Processing Core
· · · · · · · · · · · · · · Efficient, object code compatible with the 24-bit DSP56000 core family engine 81 MHz device can use a 27 MHz clock, eliminating the need for an externally generated clock signal, for instance in a DVD application Up to 44 Million Instructions Per Second (MIPS)--22.7 ns instruction cycle at 88 MHz Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block floating-point Fast Fourier Transforms (FFTs) Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories Fabricated in high-density CMOS
Memory
· · On-chip modified Harvard architecture, which permits simultaneous accesses to program and two data memories Bootstrap loading from Serial Host Interface or External Memory Interface Table 1 Memory Configuration (Word width is 24 bits)
Mode PEA 0 0 1 1 PEB 0 1 0 1 Program ROM 10.0 K 10.0 K 10.0 K 10.0 K RAM 0.5 K 1.25 K 2.0 K 2.75 K X Data ROM 3.0 K 3.0 K 3.0 K 3.0 K RAM 4.5 K 3.75 K 3.75 K 3.0 K Y Data ROM 1.75 K 1.75 K 1.75 K 1.75 K RAM 4.25 K 4.25 K 3.5 K 3.5 K Bootstrap ROM 64
MOTOROLA
DSP56009/D, Rev. 1
iii
DSP56009 Features
Peripheral and Support Circuits
· Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I2S, Sony, and Matsushita audio protocols; and two sets of SAI interrupt vectors Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words External Memory Interface (EMI), implemented as a peripheral supporting: · · · · · · · · · · Page-mode DRAMs (one or two chips): 64 K × 4, 256 K × 4, and 4 M × 4 bits SRAMs (one to four): 256 K × 8 bits Data bus may be 4 or 8 bits wide Data words may be 8, 12, 16, 20, or 24 bits wide
· ·
Four dedicated, independent, programmable General Purpose I/O (GPIO) lines On-chip peripheral registers memory mapped in data memory space Three external interrupt request pins On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock Power-saving Wait and Stop modes Fully static, HCMOS design for operating frequencies down to DC 80-pin plastic Quad Flat Pack surface-mount package; 14 × 14 × 2.20 mm (2.152.45 mm range); 0.65 mm lead pitch Complete pinout compatibility between DSP56009, DSP56004, DSP56004ROM, and DSP56007 for easy upgrades 5 V power supply
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DSP56009/D, Rev. 1
MOTOROLA
DSP56009 Product Documentation
PRODUCT DOCUMENTATION
Table 2 lists the documents that provide a complete description of the DSP56009 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2 DSP56009 Documentation
Document Name DSP56000 Family Manual DSP56009 User's Manual DSP56009 Technical Data Description of Content DSP56000 core family architecture and the 24-bit core processor and instruction set Memory, peripherals, and interfaces Electrical and timing specifications, and pin and package descriptions Order Number DSP56KFAMUM/AD DSP56009UM/AD DSP56009/D
MOTOROLA
DSP56009/D, Rev. 1
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