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Part: DSP56011PB
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Description:
Company: Motorola Semiconductor Products
Datasheet: Download DSP56011PB datasheet File size : 331 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56011/D
DSP56011
Advance Information
24-BIT DVD DIGITAL SIGNAL PROCESSOR
The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top audio decoding. The DSP56011 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with Motorola's certified software for Dolby AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use Motorola's 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/ system decoders. In addition, the DSP56011 offers switchable memory space configuration, a large user-definable Program ROM and two independent data RAMs and ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), Parallel Host Interface (HI) with Direct Memory Access (DMA) for communicating with other processors, dedicated I/O lines, on-chip Phase Lock Loop (PLL), On-Chip Emulation (OnCETM) port, and on-chip Digital Audio Transmitter (DAX). Figure 1 shows the functional blocks of the DSP56011.
IN
9 5 2 Serial Audio Interface (SAI) Serial Host Interface (SHI) Digital Audio Transmitter (DAX) Address Generation Unit PAB XAB YAB GDB PDB XDB YDB Program Program Decode Address Controller Generator Program Control Unit 4
15 Parallel Host Interface (HI) Expansion Area 24-Bit DSP56000 Core
8 General Purpose I/O (GPIO)
PR
EL
Internal Data Bus Switch OnCETM Port Clock PLL Gen. Program Interrupt Controller 3 4 EXTAL
Rev. 1
IM
IRQA, IRQB, NMI, RESET
AR
Program Memory X Data Memory
Figure 1 DSP56011 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary Information
© MOTOROLA, INC. 1996, 1997
Y
16-Bit Bus 24-Bit Bus Y Data Memory Data ALU 24 × 24 + 56 56-Bit MAC Two 56-Bit Accumulators
AA1271
DSP56011
TABLE OF CONTENTS
SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274
Data Sheet Conventions
This data sheet uses the following conventions:
PR
Examples:
Note:
EL
"asserted" "deasserted" Signal/Symbol PIN PIN PIN PIN
OVERBAR
IM
Logic State True False True False
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
DSP56011 Technical Data Sheet, Rev. 1
IN
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Preliminary Information MOTOROLA
AR
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Y
DSP56011 Features
FEATURES
Digital Signal Processing Core
· Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte
Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multi-precision arithmetic Hardware support for block-floating point Fast Fourier Transforms (FFT) Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 iii
EL
IM
PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i : i = 0 to 15), which reduces clock noise
IN
AR
Y
47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz
DSP56011 Features
Memory
· · · · · · Modified Harvard architecture allows simultaneous access to program and data memories 12800 × 24-bit on-chip Program ROM1 4096 × 24-bit on-chip X-data RAM and 3584 × 24-bit on-chip X-data ROM1 512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM 4352 × 24-bit on-chip Y-data RAM and 2048 × 24-bit on-chip Y-data ROM1
Table 1 lists the memory configurations of the DSP56011.
Table 1 DSP56011 Internal Memory Configurations
Memory Type Program RAM X data RAM Y data RAM Program ROM X data ROM Y data ROM
0.5 K 4.0 K 4.25 K
IN
1.25 K 3.25 K 4.25 K 12.5 K 3.5 K 2.0 K
No Switch (PEA = 0, PEB = 0)
Switch A (PEA = 1, PEB = 0)
IM
12.5 K 3.5 K 2.0 K
PR
iv
EL
1.These ROMs may be factory programmed with data/program provided by the application developer.
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
Switch B (PEA = 0, PEB = 1) 2.0 K 3.25 K 3.5 K 12.5 K 3.5 K 2.0 K
As much as 2304 × 24 bits of X- and Y-data RAM can be switched to Program RAM, giving a total of 2816 × 24 bits of Program RAM
Y
Switch A+B (PEA = 1, PEB = 1) 2.75 K 2.5 K 3.5 K 12.5 K 3.5 K 2.0 K
DSP56011 Features
Peripheral and Support Circuits
· SAI includes: · Two receivers and three transmitters Master or slave capability I2S, Sony, and Matshushita audio protocol implementations Two sets of SAI interrupt vectors
SHI features: Single master capability SPI and I2C protocols 10-word receive FIFO
Support for 8-, 16- and 24-bit words.
· · · · · · · · ·
DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and AES/EBU formats. Eight dedicated, independent, programmable GPIO lines
On-chip peripheral registers memory mapped in data memory space OnCE port for unobtrusive, processor speed-independent debugging Software programmable PLL-based frequency synthesizer for the core clock Power saving Wait and Stop modes
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 v
EL
5 V power supply
Fully static, HCMOS design from specified operating frequency down to dc 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
IM
IN
·
Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen General Purpose Input/Output (GPIO) lines
AR
Y
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