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Part: DSP56012DS
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Company: Motorola Semiconductor Products
Datasheet: Download DSP56012DS datasheet File size : 331 kB
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MOTOROLA
Semiconductor Technical Data
Advance Information
DSP56012/D Rev. 0, 09/98
DSP56012 24-Bit DVD Digital Signal Processor
The DSP56012 is a high-performance programmable digital signal processor (DSP) developed for digital versatile disc (DVD), high-definition television (HDTV), and advanced set-top audio decoding. The DSP56012 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with Motorola's certified software for Dolby AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use Motorola's 24bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/system decoders. In addition, the DSP56012 offers switchable memory space configuration, a large userdefinable program ROM and two independent data RAMs and ROMs, a serial audio interface (SAI), a serial host interface (SHI), a parallel host interface (HI) with Direct Memory Access (DMA) for communicating with other processors, dedicated I/O lines, an on-chip phase-locked loop (PLL), an On-Chip Emulation (OnCETM) port, and an on-chip digital audio transmitter (DAX). Figure 1-1 shows the functional blocks of the DSP56012.
15 Parallel Host Interface (HI) Expansion Area 24-Bit DSP56000 Core Internal Data Bus Switch OnCETM Port Clock PLL Gen. 3 EXTAL 4 Address Generation Unit GDB PDB XDB YDB PAB XAB YAB 8 General Purpose I/O (GPIO) 9 Serial Audio Interface (SAI) 5 Serial Host Interface (SHI) 2 Digital Audio Transmitter (DAX) 16-Bit Bus 24-Bit Bus Program Memory X Data Memory Y Data Memory
Program Interrupt Controller 4
Program Program Decode Address Controller Generator Program Control Unit
Data ALU 24 ¥ 24 + 56 Æ 56-Bit MAC Two 56-Bit Accumulators
IRQA, IRQB, NMI, RESET
AA1271
Figure 1-1. DSP56012 Block Diagram
© Motorola, Inc., 1998
Content Organization
Part 1 Introduction to the DSP56012
Refer to Section 1.1 for information on this data sheet and on the DSP56012.
1.1 Content Organization
This section outlines the information contained in this document. Part 1, Introduction to the DSP56012....... 1-2 1.1, Content Organization ... 1-2 1.2, Data Conventions ......... 1-3 Part 2, Features .. 2-1 2.1, Features of the Digital Signal Processing Core ........... 2-1 2.2, Features of the DSP56012 Memory Configuration ..... 2-1 2.3, Peripheral and Support Circuits ........... 2-2 2.4, Documentation .... 2-3 Part 3, Signal/Connection Descriptions.... 3-1 3.1, Signal Groupings.......... 3-1 Part 4, Specifications ........ 4-1 4.1, Introduction ......... 4-1 4.2, Maximum Ratings........ 4-1 4.3, Thermal Characteristics ........ 4-2 4.4, DC Electrical Characteristics ...... 4-2 4.5, AC Electrical Characteristics ...... 4-3 4.6, Internal Clocks .... 4-3 4.7, External Clock Operation............ 4-4 4.8, Phase-Locked Loop (PLL) Characteristics ......... 4-5 4.9, RESET, Stop, Mode Select, and Interrupt Timing ...... 4-5 4.10, Host Interface (HI) Timing ....... 4-7 4.11, Serial Audio Interface (SAI) Timing) ....... 4-12 4.12, Serial Host Interface (SHI) SPI Protocol Timing .... 4-15 4.13, Serial Host Interface (SHI) I2C Protocol Timing .... 4-21 4.14, Programming the Serial Clock ......... 4-22 4.15, General Purpose Input/Output (GPIO) Timing........ 4-27 4.16, Digital Audio Transmitter (DAX) Timing...... 4-28 4.17, On-Chip Emulation (OnCE) Timing......... 4-29 Part 5, Packaging .............. 5-1 5.1, Pin-Out and Package Information........ 5-1 5.2, TQFP Package Description ......... 5-1 5.3, Ordering Drawings....... 5-6 Part 6, Design Considerations ... 6-1 6.1, Thermal Design Considerations........... 6-1 6.2, Electrical Design Considerations ......... 6-2 6.3, Power Consumption Considerations .... 6-3 6.4, Power-Up Considerations ........... 6-4 6.5, Host Port Considerations ............ 6-5 Part 7, Ordering Information ..... 7-1
1-2
DSP56012 Data Sheet
Motorola
Data Conventions
1.2 Data Conventions
This data sheet uses the following conventions: · · ·
OVERBAR: used to indicate a signal that is active when pulled low (e.g., "RESET").
"Asserted" means that a high true signal (i.e., an active high) is high or that a low true signal (i.e., an active low) is low. "Deasserted" means that a high true signal is low or that a low true signal is high.
Please refer to the examples in Table 1-1.
Table 1-1. Data Conventions
Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Motorola
Introduction to the DSP56012
1-3
Data Conventions
1-4
DSP56012 Data Sheet
Motorola
Features of the DSP56012 Memory Configuration
Part 2 Features 2.1 Features of the Digital Signal Processing Core
· · · · · · · · · · · · · Efficient, object-code compatible, 24-bit DSP56000 family DSP engine 47.5 million instructions per second (MIPS) with 21.05 ns instruction cycle at 95 MHz Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multi-precision arithmetic Hardware support for block-floating point fast fourier transforms (FFT) Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i: i = 0 to 15), which reduces clock noise Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories
2.2 Features of the DSP56012 Memory Configuration
· · · · · · Modified Harvard architecture allows simultaneous access to program and data memories 15360 × 24-bit on-chip program ROM1 4096 × 24-bit on-chip X data RAM and 3584 × 24-bit on-chip X data ROM1 4352 × 24-bit on-chip Y data RAM and 2048 × 24-bit on-chip Y data ROM1 256 × 24-bit on-chip program RAM and 32 × 24-bit bootstrap ROM As much as 2304 × 24 bits of X and Y data RAM can be switched to program RAM, giving a total of 2560 × 24 bits of program RAM
Table 2-1 lists the memory configurations of the DSP56012.
Table 2-1. DSP56012 Internal Memory Configurations
Memory Type Program RAM X data RAM Y data RAM Program ROM No Switch (PEA = 0, PEB = 0) 0.25K 4.0K 4.25K 15K Switch A (PEA = 1, PEB = 0) 1.0K 3.25K 4.25K 15K Switch B (PEA = 0, PEB = 1) 1.75K 3.25K 3.5K 15K Switch A+B (PEA = 1, PEB = 1) 2.5K 2.5K 3.5K 15K
1.
These ROMs may be factory programmed with data/program provided by the application developer.
Motorola
Features
2-1
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