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Part: DSP56167DS
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Company: Motorola Semiconductor Products
Datasheet: Download DSP56167DS datasheet File size : 331 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56167/D, Rev. 1
DSP56167
Advance Information
16-BIT DIGITAL SIGNAL PROCESSOR
The general-purpose, programmable DSP56167 is an enhanced version of the DSP56166 with added features. Designed primarily for speech coding and digital communications, the DSP56167 has a built-in codec and Phase Lock Loop (PLL). This MPU-style DSP also contains memories and digital peripherals that provide a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCETM) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. This RAM-based DSP contains a 2 K × 16 Program RAM and a 4 K × 16 data RAM. The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56167. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The DSP56167 is a member of Motorola's DSP56100 family of 16-bit Digital Signal Processors (DSPs).
Port B or Host
15 7+10
IM
Bootstrap ROM 64 × 16 Program Control Unit Program Decode Controller Program Address Generator 4 RESET
Address Generation Unit Peripheral Address Generation Unit
IN
XAB1 XAB2 PAB Program RAM 2 K × 16 Data RAM 4 K × 16 XDB PDB GDB Program Interrupt Controller Data ALU 16 × 16 + 40 40-Bit MAC Two 40-Bit Accumulators MODA/IRQA MODB/IRQB MODC/IRQC
AR
External Address Bus Switch Bus Control External Data Bus Switch External Chip Enables 16 Bits
On-Chip Peripherals: Host, SSI0, SSI1, Timer GPIO, Codec Internal Data Bus Switch and Bit Manipulation Unit Clock and PLL OnCETM
EL PR
EXTAL SXFC CLKO
Codec, Port C and/or SSI0, SSI1, Timer
Figure 1 DSP56167 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
©1996, 1997 MOTOROLA, INC.
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Address 16 Port A 10 16 Data 2 AA0771
Table of Contents
TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 SIGNAL/PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1 (800) 521-6274
Data Sheet Conventions
This data sheet uses the following conventions:
PR
Examples: Note:
EL
"asserted" "deasserted" Signal/Symbol PIN PIN PIN PIN
OVERBAR
IM
Used to indicate a signal that is active when pulled low; for example, the RESET pin is active when low Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
IN
DSP56167/D, Rev. 1
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
AR
MOTOROLA
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DESIGN CONSIDERATIONS (INCLUDES NOTES FOR DSP56166 TO DSP56167 DESIGN CONVERSION) . . . . . . . . 4-1
Features
FEATURES
· Digital Signal Processing Core Up to 30 Million Instructions Per Second (MIPS) at 60 MHz with 33.3 ns instruction cycle Single-cycle 16 × 16-bit parallel Multiply-Accumulate 2 × 40-bit accumulators with extension byte
Highly parallel instruction set with unique DSP addressing modes Nested hardware DO loops including infinite loops and DO zero loop Two instruction LMS adaptive filter loop Fast auto-return interrupts
Three external interrupt request pins
Three 16-bit internal data and three 16-bit internal address buses Individual programmable wait states on the external bus for program, data, and peripheral memory spaces Programmable absolute short addressing mode Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin Peripheral Address Generation Unit (PAGU) On-chip memory-mapped peripheral registers On-Chip Emulation (OnCETM) port for unobtrusive, processor speedindependent debugging with DR line static latch with Reset
PR
MOTOROLA
EL
· Memory
IM
64 × 16-bit bootstrap ROM
Modified Harvard architecture permits simultaneous accesses to program and data memories 2 K × 16-bit on-chip Program RAM 4 K × 16-bit on-chip data RAM
External memory expansion with 16-bit address and data buses with static latches with Reset and software-controlled BG pull-down Bootstrap loading from external byte-wide Program ROM, Host Interface, or 16-bit Synchronous Serial Interface (SSI0)
IN
DSP56167/D, Rev. 1
AR
Fractional and integer arithmetic with support for multiprecision arithmetic
Y
iii
Features
·
Peripherals Up to twenty-five General Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled Byte-wide Host Interface with Direct Memory Access (DMA) support (or up to fifteen Port B GPIO lines) On-chip voice band codec, Analog-to-Digital (A/D) and Digital-toAnalog (D/A) · · Internal voltage reference (1/2 of positive power supply) and splitvoltage operation (with respect to the core) No off-chip components required
16-bit SSI support: two 4-pin ports (or up to eight Port C GPIO lines) One 16-bit timer/event counter (or two Port C GPIO lines) Double-buffered peripherals
·
PR
iv DSP56167/D, Rev. 1 MOTOROLA
EL
IM
Energy Efficient Design
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the DSP core clock with a wide input frequency range (12.2 KHz to 60 MHz) that initializes to a preset low frequency operation during hardware reset
Power-saving Wait and Stop modes Fully static, HCMOS design allows operation from 60 MHz down to DC operating frequencies 112-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
IN
Independent external chip enables BR and PEREN during Bus Master mode
AR
Y
Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56167 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): · · · · A local Motorola distributor
A Motorola Literature Distribution Center
Table 1 DSP56167 Documentation
Name DSP56100 Family Manual DSP56167 User's Manual DSP56167 Technical Data Note: Description
Detailed description of the DSP56100 family processor core and instruction set
IN
DSP56167/D, Rev. 1
Detailed functional description of the DSP56167 memory configuration, operation, and register programming DSP56167 features list and physical, electrical, timing, and package specifications
IM
PR
MOTOROLA
EL
The DSP56167 User's Manual is currently being developed and will not be available for general release until the end of the second quarter of 1997. The DSP56167 is a feature expanded, enhanced version of the DSP56166 and is entirely software compatible. Until the DSP56167 User's Manual is available, the user can refer to the DSP56166 User's Manual, order number DSP56166UM/AD for information common to both chips and Section 4 of this document for a description of the added features and enhanced capability of the DSP56167.
AR
See note below DSP56167/D
The World Wide Web (WWW) (the source for the latest information)
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Order Number DSP56100FM/AD
A Motorola semiconductor sales office
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