|
|
Part: DSP56301DS
Category:
Description:
Company: Motorola Semiconductor Products
Datasheet: Download DSP56301DS datasheet File size : 331 kB
Request For quote: Find where to buy DSP56301DS
Datasheet text preview:
MOTOROLA
Order Number: DSP56301/D Rev. 3, 1/2001
Semiconductor Products Sector Technical Data
DSP56301
24-Bit General-Purpose Digital Signal Processor
The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine providing a twofold performance increase over Motorola's popular DSP56000 core family while retaining code compatibility. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.03.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products.
52 6 6 3
Memory Expansion Area
Triple Timer Hos t I n terf ace ESSI Interface SCI Int e rf ace Program RAM 4096 × 24 bits (Default) X Data RA M 2048 × 24 bits (Default) Y Data RAM 2048 × 24 bits (Default)
Peripheral Expansion Area
A ddress Generator Unit Six- Channel DMA Unit Bootstrap ROM
YAB XAB PAB DAB
24 External A ddress Bus Switch External Bus Interface and I-Cache Control DDB Y DB
Address
14
Control
24-Bit DSP56300 Core
24 External Data Bus Switch
Data
Internal Data B us Switch EXTAL XTAL Clock Generator PLL 2 RESET PINIT/NMI Program Interr upt Controller Program Dec ode Controller MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA Program A ddres s Generator
X DB P DB GDB
Data ALU 24 × 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter
Power M anagem ent JTAG OnCETM 6
Figure 1. DSP56301 Block Diagram
© Motorola, Inc. 1996, 2001
SECTION 1 SECTION 2 SECTION 3 SECTION 4 APPENDIX A
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . A-1 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR "asser ted" "deasser ted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
DSP56301 Technical Data
FEATUR ES High-Performance DSP56300 Core
· · · · 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.03.6 V Object code compatible with the DSP56000 core Highly parallel instruction set Data Arithmetic Logic Unit (Data ALU) -- Fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC) -- 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) -- Conditional ALU instructions -- 24-bit or 16-bit arithmetic support under software control · Program Control Unit (PCU) -- Position Independent Code (PIC) support -- Addressing modes optimized for DSP applications (including immediate offsets) -- On-chip instruction cache controller -- On-chip memory-expandable hardware stack -- Nested hardware DO loops -- Fast auto-return interrupts · Direct Memory Access (DMA) -- Six DMA channels supporting internal and external accesses -- One-, two-, and three- dimensional transfers (including circular buffering) -- End-of-block-transfer interrupts -- Triggering from interrupt lines and all peripherals · Phase Lock Loop (PLL) -- Allows change of low-power Divide Factor (DF) without loss of lock -- Output clock with skew elimination · Hardware debugging support -- On-Chip Emulation (OnCETM) module -- Joint Action Test Group (JTAG) Test Access Port (TAP) -- Address Trace mode reflects internal Program RAM accesses at the external port
DSP56301 Technical Data
iii
On-Chip Memories
· Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable:
Instruction Cache1 disabled (CE = 0) enabled (CE = 1) disabled (CE = 0) enabled (CE = 1) Notes: 1. 2. Switch Mode2 disabled (MS = 0) disabled (MS = 0) enabled (MS = 1) enabled (MS = 1) Program RAM 4096 × 24 bits 3072 × 24 bits 2048 × 24 bits 1024 × 24 bits Cache 0 1024 × 24 bits 0 1024 × 24 bits X Data RAM 2048 × 24 bits 2048 × 24 bits 3072 × 24 bits 3072 × 24 bits Y Data RAM 2048 × 24 bits 2048 × 24 bits 3072 × 24 bits 3072 × 24 bits
Controlled by the Cache Enable (CE) bit in the Status Register (SR) Controlled by the Memory Select (MS) bit in the Operating Mode Register (OMR)
·
3 K × 24 bits of bootstrap ROM
Off-Chip Memory Expansion
· · · · · Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode or two 64 K × 16-bit memory spaces in 16-Bit Compatibility mode Program memory expansion to one 16 M × 24-bit words memory space in 24-Bit mode or 64 K × 16-bit in 16-Bit Compatibility mode External memory expansion port Chip Select Logic for glueless interface to SRAMs On-chip DRAM Controller for glueless interface to DRAMs
On-Chip Peripherals
· · · · · · 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to other DSP563xx buses ISA interface requires only 74LS45-style buffer Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1) Serial Communications Interface (SCI) with baud-rate generator Triple timer module Up to forty-two programmable General-Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled
Reduced Power Dissipation
· · · · Very low power CMOS design Wait and Stop low power standby modes Fully static logic, operation frequency down to 0 Hz (DC) Optimized power management circuitry (instruction-, peripheral-, and mode-dependent)
iv
DSP56301 Technical Data
TARGET APPLICATIONS
The DSP56301 is intended for general-purpose digital signal processing, particularly in multimedia and telecommunication applications, such as video conferencing and cellular telephony.
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56301 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for detailed information): · · · · A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW)
Table 1. DSP56301 Documentation
Name DSP56300 Family Manual DSP56301 User's Manual DSP56301 Technical Data Description Detailed description of the DSP56300 family processor core and instruction set Detailed functional description of the DSP56301 memory configuration, operation, and register programming DSP56301 features list and physical, electrical, timing, and package specifications Order Number DSP56300FM/AD
DSP56301UM/AD
DSP56301/D
DSP56301 Technical Data
v
Others parts begin by ds
|
|
|
