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Part: DSP56301PW100
Category:
DSPs (Digital Signal Processors)
-> DSP56300
Description: DSP56301 24-Bit General-purpose Digital Signal Processor Data Sheet
Company: Motorola Semiconductor Products
Datasheet: Download DSP56301PW100 datasheet File size : 331 kB
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Technical Data
DSP56301/D Rev. 6, 11/2002 24-Bit Digital Signal Processor
52
6
6
3 Memory Expansion Area
Triple Timer
Host Interface
ESSI
SCI
X Data Program RAM RAM 4096 × 24 bits 2048 × 24 bits (Default) (Default)
Y Data RAM 2048 × 24 bits (Default)
Peripheral Expansion Area
The DSP56301 is intended for general-purpose digital signal processing, particularly in multimedia and telecommunication applications, such as video conferencing and cellular telephony.
24
YAB XAB PAB DAB
Address Gene rato r Unit Six-Channel DMA Unit 24-Bit Bootstrap RO M DSP56300 Core
Exte rna l Address Bus Switch Exte rna l Bus Interface and I-Cache Con tro l
Addres
14
Co n -
Internal Data Bus Switch EXTAL Clo ck XTAL PLL 2 RESET PINIT/NMI Program Interrupt Controller Pro gra m Deco de Controller MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA Program Address Generator
DDB YDB XDB PDB G DB
24
External Data Bus
Power Management
JTAG OnCETM
Dat
Data ALU 24 × 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter
6
Figure 1. DSP56301 Block Diagram
The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine providing a twofold performance increase over Motorola's popular DSP56000 core family while retaining code compatibility.
Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.03.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products.
Table of Contents
DSP56301 Features........... iii Target Applications ... ........ iv Product Documentation..... iv
Chapter 1
Signal/ Connection Descriptions
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Signal Groupings.... 1-1 Power..... ........ 1-4 Ground..... 1-4 Clock ..... ........ 1-5 Phase Lock Loop (PLL) .. 1-6 External Memory Expansion Port (Port A)............ 1-6 Interrupt and Mode Control ........ ... 1-9 Host Interface (HI32) .... 1-11 Enhanced Synchronous Serial Interface 0 (ESSI0)....... 1-19 Enhanced Synchronous Serial Interface 1 (ESSI1)....... 1-21 Serial Communication Interface (SCI).. 1-23 Timers.... 1-24 JTAG/OnCE Interface ........ .... 1-25 Introduction ....... ..... 2-1 Maximum Ratings........... 2-1 Therm al Characteristics ........... ...... 2-2 DC Electrical Characteristics ......... 2-3 AC Electrical Characteristics ......... 2-4 Pin-Out and Package Information ........... 3-1 TQFP Package Description ............ 3-2 TQFP Package Mechanical Drawing .... 3-11 MAP-BGA Package Description .......... 3-12 MAP-BGA Package Mechanical Drawing .......... 3-23 Therm al Design Considerations..... 4-1 Electrical Design Considerations ............ 4-2 Power Consumption Considerations ....... 4-3 PLL Performance Issues .......... 4-4 Input (EXTAL) Jitter Requirements........ 4-5
Chapter 2
Specifications
2.1 2.2 2.4 2.5 2.6
Chapter 3
Packaging
3.1 3.2 3.3 3.4 3.5
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4 4.5
Appendix A Index
Power Consumption Benchmark
Da ta Sheet Conventions
OVERBAR "asserted" "deasserted"
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Note: Values for V IL, VOL, VIH , and VOH are defined by individual product specifications.
ii
DSP5 6301 Features
High-Performance DSP56300 Core
· 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.03.6 V · Object code compatible with the DSP56000 core with highly parallel instruction set · Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control · Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts · Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals · Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination · Hardware debugging support including On-Chip Emulation (OnCETM) module, Joint Test Action Group (JTAG) Test Access Port (TAP)
On-Chip Peripherals
· 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers · Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) · Serial communications interface (SCI) with baud rate generator · Triple timer module · Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled
On-Chip Memories
· 3 K × 24-bit bootstrap ROM · 8 K on-chip RAM total · Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM Instruction Cache X Data RAM Size Y Data RAM Size Size Size
4096 × 24 bits 3072 × 24 bits 2048 × 24 bits 1024 × 24 bits 0 1024 × 24-bit 0 1024 × 24-bit 2048 × 24 bits 2048 × 24 bits 3072 × 24 bits 3072 × 24 bits 2048 × 24 bits 2048 × 24 bits 3072 × 24 bits 3072 × 24 bits
Instruction Cache
disabled enabled disabled enabled
Sw itch Mode
disabled disabled enabled enabled
iii
Off-Chip Memory Expansion
· Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode or two 64 K × 16-bit memory spaces in 16-Bit Compatibility mode · Program memory expansion to one 16 M × 24-bit words memory space in 24-Bit mode or 64 K × 16-bit in 16-Bit Compatibility mode · External memory expansion port · Chip Select Logic for glueless interface to SRAMs · On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Reduced Power Dissipation
· · · · Very low-power CMOS design W ait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)
Packaging
The DSP56301 is available in a 208-pin thin quad flat pack (TQFP) or a 252-pin molded array process-ball grid array (MAP-BGA) package.
Target Applications
Examples of target applications include: · · · · · W ireless and wireline infrastructure applications Multi-channel wireless local loop systems DSP resource boards High-speed modem banks Packet telephony
Product Documentation
The three documents listed in the following table are required for a complete description of the DSP56301 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for detailed information.) · · · · A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. DSP56301
N a me
DSP56300 Family Manual DSP56301 User's Manual DSP56301 Technical Data
Documentation
Order Number
D SP56300FM/AD D SP56301UM/D D SP56301/D
Description
D etailed description of the DSP56300 family processor core and instruction set D etailed functional description of the DSP56301 memory configuration, operation, and register programming D SP56301 features list and physical, electrical, timing, and package specifications
iv
Chapter 1
Signal/ Connection Descriptions
1.1 Signal Groupings
The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated in Figure 1-1.. The DSP56301 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1. DSP56301 Functional Signal Groupings
Number of Signals by Package Type MAPBGA
45 38 2 3 24 24 15 5 52 12 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-11 Table 1-12 and Table 1-13 Table 1-14 Table 1-15 Table 1-16
Functional Group
Detailed Description
TQFP
Power (VCC) 1 Ground (GND)1 Clock PLL Address Bus Port A 2 Data Bus Bus Control Interr upt and Mode Control Host Interface (HI32) Enhanced Synchronous Serial Interface (ESSI) Port B3 Ports C and D4 24 15 5 52 12 25 26 2 3 24
Serial Communication Interface (SCI) Timer JTAG/OnCE Port Notes: 1.
Port E5
3 3 6
3 3 6
2. 3. 4. 5. 6.
The number of available power and ground signals is package-dependent. In the TQFP package specific pins are dedicated internally to device subsystems. In the MAP-BGA package, power and ground connections (except those providing PLL power) connect to internal power and ground planes, respectively. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI32 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See Chapter 3 for details.
1-1
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