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Part: DSP56303PV100
Category:
DSPs (Digital Signal Processors)
-> DSP56300
Description: DSP56303 24-Bit General-purpose Digital Signal Processor Data Sheet
Company: Motorola Semiconductor Products
Datasheet: Download DSP56303PV100 datasheet File size : 331 kB
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Technical Data
DSP56303/D Rev. 8, 4/2003 24-Bit Digital Signal Processor
16
6
6
3 Memory Expansion Area
Triple Timer
HI0 8
ESSI
SC I
PrograM RAM 4096 × 24 bits (default) PM_EB
X Data RA M 2048 × 24 bits (defa ult) XM_EB
Y Data RAM 20 48 × 24 bits (de fault ) YM_EB
PIO_EB
The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/ fax processing, video conferencing, audio applications, control, and general digital signal processing.
EXTAL XTAL
Periph era l Expa nsion Area
Address Generation Unit Six-Channe l DMA Unit Boo tstrap RO M
YAB XAB PAB DAB 24-Bit
18 External Address Bus Address Switch External Bus 13 Interface and Inst. Cach e Co ntrol Control Externa l Data Bus Switch 24 Da ta
DSP56 300 Core DDB YDB XDB PDB GDB
Inte rna l Data Bus Switch Clock Generator PLL 2 RESET PINI T/ NMI
Program In terrup t Controller
Program Decode Co ntroller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
Program Add ress Ge nerator
24 × 24 + 56 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter
Data ALU
Power Management JTAG OnCETM
5
DE
Figure 1. DSP56303 Block Diagram
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine providing a twofold performance increase over Motorola's popular DSP56000 core family while retaining code compatibility.
Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MIPS using an internal 100 MHz clock at 3.03.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products.
Table of Contents
DSP56303 Features........... iii Target Applications ........... iv Product Documentation..... iv
Chapter 1
Signal/ Connection Descriptions
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Signal Groupings.... 1-1 Power....... 1-3 Ground..... 1-3 Clock ....... 1-4 PLL .......... 1-4 External Memory Expansion Port (Port A)............ 1-5 Interrupt and Mode Control ........... 1-8 Host Interface (HI08) ...... 1-9 Enhanced Synchronous Serial Interface 0 (ESSI0)....... 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1)....... 1-14 Serial Communication Interface (SCI).. 1-16 Timers.... 1-17 JTAG and OnCE Interface ........... 1-18 Introduction ............ 2-1 Maximum Ratings........... 2-1 Therm al Characteristics .. 2-2 DC Electrical Characteristics ......... 2-3 AC Electrical Characteristics ......... 2-4 Pin-Out and Package Information ........... 3-1 TQFP Package Description ............ 3-2 TQFP Package Mechanical Drawing ...... 3-9 MAP-BGA Package Description .......... 3-10 MAP-BGA Package Mechanical Drawing .......... 3-19 Therm al Design Considerations..... 4-1 Electrical Design Considerations ............ 4-2 Power Consumption Considerations ....... 4-4 PLL Performance Issues .......... 4-5 Input (EXTAL) Jitter Requirements........ 4-5
Chapter 2
Specifications
2.1 2.2 2.4 2.5 2.6
Chapter 3
Packaging
3.1 3.2 3.3 3.4 3.5
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4 4.5
Appendix A Index
Power Consumption Benchmark
Da ta Sheet Conventions
OVERBA R "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Note: Values for V IL, VOL, VIH , and VOH are defined by individual product specifications.
ii
DSP5 6303 Features
High-Performance DSP56300 Core
· 100 million instructions per second (MIPS) with a 100 MHz clock at 3.3 V nominal · Object code compatible with the DSP56000 core with highly parallel instruction set · Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control · Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts · Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals · Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination · Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action Group (JTAG) Test Access Port (TAP)
On-Chip Peripherals
· Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs · Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) · Serial communications interface (SCI) with baud rate generator · Triple timer module · Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled
On-Chip Memories
· 192 × 24-bit bootstrap ROM · 128 K RAM total · Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM Size
4096 × 24-bit 3072 × 24-bit 2048 × 24-bit 1024 × 24-bit
Instruction Cache Size
0 1024 × 24-bit 0 1024 × 24-bit
X Data RAM Size
2048 × 24-bit 2048 × 24-bit 3072 × 24-bit 3072 × 24-bit
Y Data RAM Size
2048 × 24-bit 2048 × 24-bit 3072 × 24-bit 3072 × 24-bit
Instruction Cache
disabled enabled disabled enabled
Switch Mode
disabled disabled enabled enabled
iii
Off-Chip Memory Expansion
· Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines · Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines · External memory expansion port · Chip Select Logic for glueless interface to static random access memory (SRAMs) · On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Reduced Power Dissipation
· · · · Very low-power CMOS design W ait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)
Packaging
The DSP56303 is available in a 144-pin TQFP package or a 196-pin MAP-BGA package.
Target Applications
· · · · Multi-line voice/data/fax processing Video conferencing Audio applications Control
Product Documentation
The three documents listed in the following table are required for a complete description of the DSP56303 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for details.) · · · · A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. DSP56303
N a me
DSP56300 Family Manual DSP56303 User's Manual DSP56303 Technical Data
Documentation
Order Number
D SP56300FM/AD D SP56303UM/D D SP56303/D
Description
D etailed description of the DSP56300 family processor core and instruction set D etailed functional description of the DSP56303 memory configuration, operation, and register programming D SP56303 features list and physical, electrical, timing, and package specifications
iv
Chapter 1
Signal/ Connection Descriptions
1.1 Signal Groupings
The DSP56303 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1. DSP56303 Functional Signal Groupings
Number of Signals Functional Group TQFP
Power (VCC) Ground (GND) Clock PLL Address bus Data bus Bus control Interr upt and mode control Host interface (HI08) Enhanced synchronous serial interface (ESSI) Serial communication interface (SCI) Timer OnCE/JTAG Port Notes: 1. 2. 3. 4. 5. Port B2 D3 Port A1 18 19 2 3 18 24 13 5 16 12 3 3 6
M APBGA
18 66 2 3 18 24 13 5 16 12 3 3 6
Ports C and Port E4
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA package that are not used. These are designated as no connect (NC) in the package description (see Chapter 3).
Note:
This chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. Refer to the DSP56303 User's Manual for details on these configuration registers.
1-1
Others parts begin by ds
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