Details, datasheet, quote on part number: KMPC8250ACZUMHBB
PartKMPC8250ACZUMHBB
CategoryMicroprocessors => 32 bit => PowerPC™ Processors->Integrated Communicatio
TitlePowerPC™ Processors->Integrated Communicatio
DescriptionMPC8250 Hardware Specifications
CompanyMotorola Semiconductor Products
DatasheetDownload KMPC8250ACZUMHBB datasheet
  

 

Features, Applications

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8250 PowerQUICC IITM communications processor. The following topics are addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical and Thermal Characteristics" Section 1.2.1, "DC Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "Power Considerations" Section 1.2.4, "AC Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Bus Mode" Section 1.3.2, "PCI Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page

The MPC8250 is available in two packages--the standard ZU package (480 TBGA) and an alternate VR package (516 PBGA)--as described in Section 1.4, "Pinout," and Section 1.5, "Package Description." For more information on VR packages, contact your Motorola sales office. Note that throughout this document references to the MPC8250 are inclusive of its VR version unless otherwise specified.

NOTE: Document Revision History Changes to this document are summarized in Table 23 on page 56.
Features

16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM 4 Virtual IDMAs System Functions Interrupt Controller 32 Kbytes Dual-Port RAM Serial DMAs Clock Counter 60x Bus

Footprint-compatible with the MPC8260 Dual-issue integer core A core version of the EC603e microprocessor System core microprocessor supporting frequencies of 150200 MHz Separate 16-Kbyte data and instruction caches: Four-way set associative Physically addressed LRU replacement algorithm PowerPC architecture-compliant memory management unit (MMU) Common on-chip processor (COP) test interface High-performance (4.45.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz) Supports bus snooping for data cache coherency Floating-point unit (FPU)

Separate power supply for internal logic (1.8 V) and for I/O (3.3V) Separate PLLs for G2 core and for the CPM G2 core and CPM can run at different frequencies for power/performance optimization Internal core/bus clock multiplier that provides ratios Internal CPM/bus clock multiplier that provides ratios 64-bit data and 32-bit address 60x bus Bus supports multiple master designs Supports single- and four-beat burst transfers 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus Single-master bus, supports external slaves Eight-beat burst transfers 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge Programmable host bridge and agent 32-bit data bus, 66 MHz, 3.3 V Synchronous and asynchronous 60x and PCI clock modes All internal address space available to external PCI host DMA for memory block transfers PCI-to-60x address remapping

System interface unit (SIU) Clock synthesizer Reset controller Real-time clock (RTC) register Periodic interrupt timer Hardware bus monitor and software watchdog timer IEEE 1149.1 JTAG test access port

Twelve-bank memory controller Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals Byte write enables and selectable parity generation 32-bit address decodes with programmable bank size Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) Dedicated interface logic for SDRAM

CPU core can be disabled and the device can be used in slave mode to an external core

 

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