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Details, datasheet, quote on part number:KMPC866TZP133
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Advance Information
MPC866EC/D Rev. 1.4, 8/2003 MPC866/859 Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC866/859 family (refer to Table 1 for a list of devices). The MPC866P is the superset device of the MPC866/859 family. This document describes pertinent electrical and physical characteristics of the MPC8245. For functional characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual (MPC866UM/D). This document contains the following topics:
Topic Page
Section 1, "Overview" Section 2, "Features" Section 3, "Maximum Tolerated Ratings" Section 4, "Thermal Characteristics" Section 5, "Power Dissipation" Section 6, "DC Characteristics" Section 7, "Thermal Calculation and Measurement" Section 8, "Power Supply and Power Sequencing" Section 9, "Layout Practices" Section 10, "Bus Signal Timing" Section 11, "IEEE 1149.1 Electrical Specifications" Section 12, "CPM Electrical Characteristics" Section 13, "UTOPIA AC Electrical Specifications" Section 14, "FEC Electrical Characteristics" Section 15, "Mechanical Data and Ordering Information" Section 16, "Document Revision History"
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Overview
The MPC866/859 is a derivative of Motorola's MPC860 PowerQUICCTM family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC866/859/859DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.
Features
Table 1 shows the functionality supported by the members of the MPC866/859 family.
Table 1. MPC866 Family Functionality
Cache Part Instruction MPC866P MPC866T MPC859P MPC859T MPC859DSL MPC852T 3
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Ethernet SCC Data 8 Kbytes 4 Kbytes 8 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 10T Up to 4 Up to 4 1 1 1 2 10/100 1 1 1 1 1 1 4 4 1 1 11 2 2 2 2 2 12 1 SMC
16 Kbytes 4 Kbytes 16 Kbytes 4 Kbytes 4 Kbytes 4 KBytes
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot Assigner (TSA). 2 On the MPC859DSL, the SMC (SMC1) is for UART only. 3 For more details on the MPC852T, please refer to the MPC852T Hardware Specifications.
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Features
Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) -- The core performs branch prediction with conditional prefetch, without conditional execution -- 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1) 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets; 4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets. 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets. Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. -- MMUs with 32-entry TLB, fully associative instruction and data TLBs -- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups. -- Advanced on-chip-emulation debug mode The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The MPC866/859 adds major new features available in 'enhanced SAR' (ESAR) mode, including the following: -- Improved operation, administration, and maintenance (OAM) support -- OAM performance monitoring (PM) support
The following list summarizes the key MPC866/859 features:
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MPC866/859 Hardware Specifications
MOTOROLA
Features
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Multiple APC priority levels available to support a range of traffic pace requirements ATM port-to-port switching capability without the need for RAM-based microcode Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability Optional statistical cell counters per PHY UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level 1 specification is also supported.) Multi-PHY support on the MPC866, MPC859P, and MPC859T Four PHY support on the MPC866/859 -- Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode -- Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a 'split' bus -- AAL2/VBR functionality is ROM-resident. Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) Thirty-two address lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank -- Up to 30 wait states programmable per memory bank -- Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other memory devices. -- DRAM controller programmable to support most size and speed memory interfaces -- Four CAS lines, four WE lines, and one OE line -- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) -- Variable block sizes (32 Kbytes256 Mbytes) -- Selectable write protection -- On-chip bus arbitration logic General-purpose timers -- Four 16-bit timers cascadable to be two 32-bit timers -- Gate mode can enable/disable counting -- Interrupt can be masked on reference match and event capture Fast Ethernet controller (FEC) -- Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA multiplexed bus System integration unit (SIU) -- Bus monitor -- Software watchdog -- Periodic interrupt timer (PIT) -- Low-power stop mode -- Clock synthesizer -- Decrementer and time base from the PowerPC architecture -- Reset controller
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MOTOROLA
MPC866/859 Hardware Specifications
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