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Details, datasheet, quote on part number:KXPC7441RX700LG
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Advance Information
MPC7441EC/D Rev. 0, 10/2001 MPC7441 RISC Microprocessor Hardware Specifications
The MPC7441 is a reduced instruction set computing (RISC) microprocessor that implements the PowerPC instruction set architecture. This document describes pertinent electrical and physical characteristics of the MPC7441. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family User's Manual. This document contains the following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "Comparison with the MPC7400" Section 1.4, "General Parameters" Section 1.5, "Electrical and Thermal Characteristics" Section 1.6, "Pin Assignments" Section 1.7, "Pinout Listings for the 360 CBGA Package" Section 1.8, "Package Description" Section 1.9, "System Design Information" Section 1.10, "Document Revision History" Section 1.11, "Ordering Information" To locate any published updates for this document, refer to the website at http://www.motorola.com/semiconductors
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1.1
Overview
The MPC7441 is the third implementation of the fourth generation (G4) microprocessors from Motorola. The MPC7441 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7441 consists of a processor core and a 256-Kbyte L2. Figure 1 shows a block diagram of the MPC7441. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources.
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
2 MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Figure 1. MPC7441 Block Diagram
Additional Features · Time Base Counter/Decrementer · Clock Multiplier · JTAG/COP Interface · Thermal/Power Management · Performance Monitor
96-Bit (3 Instructions)
Instruction Unit Branch Processing Unit BTIC (128-Entry) BHT (2048-Entry) CT R Fetcher
Instruction Queue (12-Word)
Instruction MMU SRs (Shadow) 128-Entry ITLB
128-Bit (4 Instructions)
Tags
IBAT Array LR Dispatch Unit Data MMU SRs (Original) VR Issue (4-Entry/2-Issue) GPR Issue (6-Entry/3-Issue) FPR Issue (2-Entry/1-Issue) 128-Entry DTLB Tags
32-Kbyte I Cache
32-Kbyte D Cache
DBAT Array
Reservation Stations (2-Entry) Vector Touch Queue GPR File 16 Rename Buffers
EA
Load/Store Unit Vector Touch Engine + (EA Calculation) Finished Stores L1 Castout PA FPR File 16 Rename Buffers Reservation Stations (2)
Reservation Reservation Reservation Reservation Station Station Station Station
VR File 16 Rename Buffers
Reservation Stations (2)
Reservation Reservation Reservation Station Station Station
Vector Permute Unit
Vector Integer Unit 2
Vector Integer Unit 1
Vector FPU
Integer Unit 2 x÷
Innneeger t t ger I I et ger Unnntit22 U iti 1 U (3) +++
FloatingPoint Unit + x÷ FPSCR
L1 Push Completed Stores
32-Bit 128-Bit 128-Bit
32-Bit
32-Bit
Load Miss
64-Bit
64-Bit
Completion Unit Completion Queue (16-Entry) Memory Subsystem System Bus Interface L2 Prefetch (3) Bus Store Queue Push Castout Queue (9) L2 Store Queue (L2SQ) Snoop Push/ Interventions 256-Kbyte Unified L2 Cache/Cache Controller Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status L1 Service Queues L1 Store Queue (LSQ) L1 Load Queue (LLQ) L1 Load Miss (5) Instruction Fetch (2) Cacheable Store Request (1)
L1 Castouts (4)
Bus Accumulator Completes up to three instructions per clock 36-Bit Address Bus 64-Bit Data Bus
Features
1.2
Features
This section summarizes features of the MPC7441 implementation of the PowerPC architecture. Major features of the MPC7441 are as follows: Major features of the MPC7441 are as follows: · High-performance, superscalar microprocessor -- As many as 4 instructions can be fetched from the instruction cache at a time -- As many as 3 instructions can be dispatched to the issue queues at a time -- As many as 12 instructions can be in the instruction queue (IQ) -- As many as 16 instructions can be at some stage of execution simultaneously -- Single-cycle execution for most instructions -- One instruction per clock cycle throughput for most instructions -- Seven-stage pipeline control · Eleven independent execution units and three register files -- Branch processing unit (BPU) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction-- not-taken, strongly not-taken, taken, strongly taken Up to three outstanding speculative branches Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. 8-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions. -- Four integer units (IUs) that share 32 GPRs for integer operands Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. -- Five-stage FPU and a 32-entry FPR file Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Hardware support for denormalized numbers Thirty-two 64-bit FPRs for single- or double-precision operands -- Four vector units and 32-entry vector register file (VRs) Vector permute unit (VPU)
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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