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Details, datasheet, quote on part number:KXPC7451RX667LG
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Advance Information
MPC7451EC/D Rev. 0.1, 11/2001 MPC7451 RISC Microprocessor Hardware Specifications
The MPC7451 is a reduced instruction set computing (RISC) microprocessor that implements the PowerPC instruction set architecture. This document describes pertinent electrical and physical characteristics of the MPC7451. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family User's Manual. This document contains the following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "Comparison with the MPC7400" Section 1.4, "General Parameters" Section 1.5, "Electrical and Thermal Characteristics" Section 1.6, "Pin Assignments" Section 1.7, "Pinout Listings for the 483 CBGA Package" Section 1.8, "Package Description" Section 1.9, "System Design Information" Section 1.10, "Document Revision History" Section 1.11, "Ordering Information" To locate any published updates for this document, refer to the website at http://www.motorola.com/semiconductors
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1.1
Overview
The MPC7451 is the third implementation of the fourth generation (G4) microprocessors from Motorola. The MPC7451 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7451 consists of a processor core, a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface. Figure 1 shows a block diagram of the MPC7451. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data. Note that the MPC7451 is a footprint-compatible, drop-in replacement in a MPC7450 application as long as the core power supply is 1.6 V.
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
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Instruction Unit Branch Processing Unit Fetcher Tags IBAT Array BHT (2048-Entry) Dispatch Unit Data MMU SRs (Original) VR Issue (4-Entry/2-Issue) DBAT Array GPR Issue (6-Entry/3-Issue) FPR Issue (2-Entry/1-Issue) 128-Entry DTLB Tags LR BTIC (128-Entry) CT R Instruction Queue (12-Word) SRs (Shadow) 128-Entry ITLB Instruction MMU 128-Bit (4 Instructions) 32-Kbyte I Cache 32-Kbyte D Cache Reservation Stations (2-Entry) EA Load/Store Unit Vector Touch Engine + (EA Calculation) Finished Stores L1 Castout PA FPR File 16 Rename Buffers Reservation Stations (2) VR File 16 Rename Buffers Integer Unit 2 x÷ +++ 32-Bit 32-Bit Innneeger t t ger I I et ger Unnntit22 U iti 1 U (3) 16 Rename Buffers Reservation Stations (2) GPR File Reservation Reservation Reservation Station Station Station Vector Touch Queue Vector Integer Unit 1 Vector FPU FloatingPoint Unit L1 Push Completed Stores + x÷ FPSCR Load Miss 64-Bit 64-Bit 32-Bit 128-Bit 128-Bit L3 Cache Controller Line Block 0/1 Tags Status L3CR Bus Accumulator 18-Bit Address External SRAM (1 or 2 Mbytes) Bus Accumulator 36-Bit Address Bus 64-Bit Data Bus 64-Bit Data (8-Bit Parity) Memory Subsystem System Bus Interface L2 Prefetch (3) Bus Store Queue Push Castout Queue (9) L2 Store Queue (L2SQ) Snoop Push/ Interventions L1 Castouts (4) 256-Kbyte Unified L2 Cache/Cache Controller Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status L1 Service Queues L1 Store Queue (LSQ) L1 Load Queue (LLQ) L1 Load Miss (5) Instruction Fetch (2) Cacheable Store Request (1)
Additional Features · Time Base Counter/Decrementer · Clock Multiplier · JTAG/COP Interface · Thermal/Power Management · Performance Monitor
96-Bit (3 Instructions)
Reservation Reservation Reservation Reservation Station Station Station Station
Figure 1. MPC7451 Block Diagram
Vector Permute Unit
Vector Integer Unit 2
Completion Unit
MPC7451 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Completion Queue (16-Entry)
MOTOROLA
Completes up to three instructions per clock
Features
1.2
Features
This section summarizes features of the MPC7451 implementation of the PowerPC architecture. Major features of the MPC7451 are as follows: Major features of the MPC7451 are as follows: · High-performance, superscalar microprocessor -- As many as 4 instructions can be fetched from the instruction cache at a time -- As many as 3 instructions can be dispatched to the issue queues at a time -- As many as 12 instructions can be in the instruction queue (IQ) -- As many as 16 instructions can be at some stage of execution simultaneously -- Single-cycle execution for most instructions -- One instruction per clock cycle throughput for most instructions -- Seven-stage pipeline control · Eleven independent execution units and three register files -- Branch processing unit (BPU) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction-- not-taken, strongly not-taken, taken, strongly taken Up to three outstanding speculative branches Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. 8-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions. -- Four integer units (IUs) that share 32 GPRs for integer operands Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. -- Five-stage FPU and a 32-entry FPR file Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Hardware support for denormalized numbers Thirty-two 64-bit FPRs for single- or double-precision operands -- Four vector units and 32-entry vector register file (VRs) Vector permute unit (VPU)
MOTOROLA
MPC7451 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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