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Part: MC12181D
Category:
Communication
Description: 125 - 1000 MHZ Frequency Synthesizer
Company: Motorola Semiconductor Products
Datasheet: Download MC12181D datasheet File size : 51 kB
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125-1000 MHz Frequency Synthesizer
The MC12181 is a monolithic bipolar synthesizer integrating a high performance prescaler, programmable divider, phase/frequency detector, charge pump, and reference oscillator/buffer functions. The device is capable of synthesizing a signal which is 25 to 40 times the input reference signal. The device has a 4bit parallel interface to set the proper total multiplication which can range from 25 to 40. When combined with an external passive loop filter and VCO, the MC12181 serves as a complete PLL subsystem.
MC12181
125 1000 MHZ FREQUENCY SYNTHESIZER
SEMICONDUCTOR TECHNICAL DATA
· · · · · · · · · ·
2.7 to 5.5 V Operation Low power supply current of 4.25 mA typical On chip reference oscillator/buffer supporting wide frequency operating range from 5 to 25 MHz 4bit parallel interface for programming divider (N = 25 .... 40) Wide 125 1000 MHz frequency of operation Digital phase/frequency detector with linear transfer function Balanced Charge Pump Output Space efficient 16 lead SOIC package Operating Temperature Range of 40 to 85°C > 1000 V ESD Protection (I/O to Ground, I/O to VCC)
D SUFFIX PLASTIC PACKAGE CASE 751B (SO16)
16 1
The device is suitable for applications where a fixed local oscillator (LO) needs to be synthesized or where a limited number of LO frequencies need to be generated. The device also has auxiliary open emitter outputs (Pout and Rout) for observing the inputs to the phase detector for verification purposes. In normal use the pins should be left open. The Reset input is normally LOW. When this input is placed in the HIGH state the reference prescaler is reset and the charge pump output (Do) is placed in the OFF state. The 4bit programming interface maps into divider states ranging from 25 to 40. A is the LSB and D is the MSB. The data inputs (A,B,C, and D) are CMOS compatible and have pullup resistors. The inputs can be tied directly to Vcc or Ground for programming or can be interfaced to an external data latch/register. Table 1 below has a mapping of the programming states. Table 1. Programming States
D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H Divider 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN CONNECTIONS
OSCin 1 OSCout 2 VP 3 VCC 4 Do 5 GND 6 Fin 7 Fin 8 (Top View)
16 A 15 B 14 C 13 D 12 Pout 11 Reset 10 Rout 9 GND
ORDERING INFORMATION
Device MC12181D Operating Temperature Range TA = 40° to +85°C Package SO16
© Motorola, Inc. 1997
Rev 2
MC12181
Figure 1. MC12181 Programmable Synthesizer
A B C D
DECODE LOGIC Fin Fin Reset PHASE/FREQ DETECTOR OSCin OSCout CHARGE PUMP
DIVIDE BY 8 PRESCALER
PROGRAMMABLE DIVIDER (25 40)
DIVIDE BY 2
Pout
Do
CRYSTAL OSCILLATOR/BUFFER
DIVIDE BY 8 PRESCALER
Rout
PIN NAMES
Pin No. 1 Pin OSCin Function An external parallel resonant, fundamental crystal is connected between OSCin and OSCout to form an internal reference crystal oscillator. External capacitors C1 and C2 are required to set the proper crystal load capacitance and oscillator frequency (Figure 2). For an external reference oscillator, a signal is accoupled into the OSCin pin. In either mode a 50 k resistor MUST be connected between OSCin and OSCout. Oscillator output, for use with an external crystal as shown in Figure 2. Positive power supply for charge pump. VP MUST be greater than or equal to VCC. Bypassing should be placed as close as possible to this pin and be connected directly to the ground plane. Positive power supply. Bypassing should be placed as close as possible to this pin and be connected directly to the ground plane. Single ended phase/frequency detector output. Threestate current sink/source output for use as a loop error signal when combined with an external low pass filter. The phase/frequency detector is characterized by a linear transfer function. Ground. This pin should be directly tied to the ground plane. Prescaler input The VCO signal is accoupled into the Fin Pin. Complementary prescaler input This pin should be capacitively coupled to ground. Ground. This pin should be directly tied to the ground plane. Open emitter test point used to verify proper operation of the reference divider chain. In normal operation this pin should be left OPEN. Test pin used to clear the prescalers (Reset = H). When the Reset is in the HIGH state, the charge pump output is disabled. The Reset input has an internal pulldown. In normal operation it can be left open or tied to ground. Open emitter test point used to verify proper operation of the programmable divider chain. The output is a divideby2 version of the programmable input to the phase/frequency detector. In normal operation this pin should be left OPEN. Digital control inputs for setting the value of the programmable divider. A is the LSB and D is the MSB. In normal operation these pins can be tied to VCC and/or ground to program a fixed divide or they can be driven by a CMOS logic level when used in a programmable mode. There is an internal pullup resistor to VCC on each input.
2 3 4 5
OSCout VP VCC Do
6 7 8 9 10 11 12
GND Fin Fin GND Rout Reset Pout
13 14 15 16
D C B A
2
MOTOROLA RF/IF DEVICE DATA
MC12181
Figure 2. Typical Applications Example
R1 is 50 k (Nominal) C1/C2 depend on crystal selected
1 C1 C2 R1 2
OSCin OSCout VP VCC Do GND Fin Fin
A 16 B 15 C 14 D 13 Pout 12 Reset 11 Rout 10 GND 9 NC NC
VP VCC Passive Filter
0.1 µF 0.1 µF
3 100 pF 4 100 pF 5 6 1000 pF
CMOS Logic Levels or VCC and/or GND
VCO 1000 pF
7 8
Figure 3. Typical Passive Loop Filter Topology
RX Do RO CO CA CX VCO Input
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Range Maximum Supply Range Maximum Charge Pump Voltage Temperature Ambient Storage Temperature Maximum Input Signal (Any Pin) Symbol VCC VCCmax VPmax TA TSTG Vinmax Min 2.7 40 65 Max 5.5 6.0 VCC to +6.0 85 150 VCC+0.5 V Unit VDC VDC VDC °C °C VDC
MOTOROLA RF/IF DEVICE DATA
3
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