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Part: MC12202D
Category:
Communication
Description: Mecl PLL Components Serial Input PLL Frequency Synthesizer
Company: Motorola Semiconductor Products
Datasheet: Download MC12202D datasheet File size : 119 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Serial Input PLL Frequency Synthesizer
The MC12202 is a 1.1GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulseswallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications. Motorola's advanced Bipolar MOSAICTM V technology is utilized for low power operation at a minimum supply voltage of 2.7V. The device is designed for operation over 2.7 to 5.5V supply range for input frequencies up to 1.1GHz with a typical current drain of 6.5mA. The low power consumption makes the MC12202 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 64/65 or 128/129 divide ratio. For additional applications information, two InterActiveApNoteTM d o c u m e n t s containing software (based on a Microsoft Excel spreadsheet) and an Application Note are available. Please order DK305/D and DK306/D from the Motorola Literature Distribution Center.
MC12202
MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer
16 1
· Low Power Supply Current of 5.8mA Typical for ICC and 0.7mA Typical
for IP
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05
· Supply Voltage of 2.7 to 5.5V · Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or
128/129
16 1
· OnChip Reference Oscillator/Buffer · Programmable Reference Divider Consisting of a Binary 14Bit
Programmable Reference Counter
M SUFFIX PLASTIC SOIC PACKAGE CASE 96601
· Programmable Divider Consisting of a Binary 7Bit Swallow Counter
and an 11Bit Programmable Counter
· Phase/Frequency Detector With Phase Conversion Function · Balanced Charge Pump Outputs · Dual Internal Charge Pumps for Bypassing the First Stage of the Loop
Filter to Decrease Lock Time
20 1
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E02
· Outputs for External Charge Pump · Operating Temperature Range of 40°C to +85°C · Space Efficient Plastic Surface Mount SOIC or TSSOP Packages · The MC12202 Is Pin Compatible With the Fujitsu MB1502 or MB1511
MAXIMUM RATINGS* Symbol
VCC VP Tstg
Parameter
Power Supply Voltage, Pin 4 (Pin 5 in 20lead package) Power Supply Voltage, Pin 3 (Pin 4 in 20lead package) Storage Temperature Range
Value
0.5 to +6.0 VCC to +6.0 65 to +150
Unit
VDC VDC °C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.
1/97
© Motorola, Inc. 1997
1
REV 4
MC12202
R 16 P 15 fOUT BISW 14 13 FC 12 LE 11 DATA 10 CLK 9
Pinout: 16Lead Packages (Top View)
1
2
3
4 VCC
5 Do FC 15
6 GND LE 14
7 LD DATA 13
8 fIN NC 12 CLK 11
OSCin OSCout VP R 20 NC 19 P 18
fOUT BISW 17 16
Pinout: 20Lead Package (Top View)
1 OSCin
2
3
4 VP
5 VCC
6 Do
7 GND
8 LD
9 NC
10 fIN
NC OSCout
PIN NAMES
Pin OSCin OSCout VP VCC Do GND LD fIN CLK DATA LE I/O I O -- -- O -- O I I I I Function Oscillator input. A crystal is connected between OSCin and OSCout. An external source can be AC coupled into this input Oscillator output. Pin should be left open if external source is used Power supply for charge pumps (VP should be greater than or equal to VCC) VP provides power to the Do, BISW and P outputs Power supply voltage input. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge pump output. Do remains on at all times Ground Lock detect, phase comparator output Prescaler input. The VCO signal is ACcoupled into this pin Clock input. Rising edge of the clock shifts data into the shift registers Binary serial data input Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data stored in the shift register is transferred into the appropriate latch (depending on the level of control bit). Also, when LE is HIGH or OPEN, the output of the second internal charge pump is connected to the BISW pin Phase control select (with internal pull up resistor). When FC is LOW, the characteristics of the phase comparator and charge pump are reversed. FC also selects fp or fr on the fOUT pin Analog switch output. When LE is HIGH or OPEN ("analog switch is ON") the output of the second charge pump is connected to the BISW pin. When LE is LOW, BISW is high impedance Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable reference divider output; when FC is LOW, fOUT=fp, programmable divider output Output for external charge pump. Standard CMOS output level Output for external charge pump. Standard CMOS output level No connect 16Lead Pkg Pin No. 1 2 3 4 5 6 7 8 9 10 11 20Lead Pkg Pin No. 1 3 4 5 6 7 8 10 11 13 14
FC
I
12
15
BISW
O
13
16
fOUT P R NC
O O O --
14 15 16 --
17 18 20 2, 9, 12, 19
MOTOROLA
2
HIPERCOMM BR1334 -- Rev 4
MC12202
15BIT SHIFT REGISTER 15
15BIT LATCH 14 1
PROGRAMMABLE REFERENCE DIVIDER OSCin OSCout CRYSTAL OSCILLATOR 14BIT REFERENCE COUNTER fr PHASE/FREQUENCY DETECTOR CHARGE PUMP 1 LE LE DATA 7 CLK 7BIT LATCH 7 CONTROL BIT DATA 18BIT SHIFT REGISTER 11 DIVIDER OUTPUT MUX fOUT LD P R
FC
Do
CHARGE PUMP 2
BISW
11BIT LATCH 11
fIN
PRESCALER 64/65 or 128/129
PROGRAMMABLE DIVIDER 7BIT SWALLOW ACOUNTER 11BIT PROGRAMMABLE NCOUNTER
fp
CONTROL LOGIC
Figure 1. MC12202 Block Diagram
HIPERCOMM BR1334 -- Rev 4
3
MOTOROLA
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