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Part: MC12430FN
Category:
Timing Circuits
-> Clock Synthesizers
Description: High Frequency PLL Clock Generator
Company: Motorola Semiconductor Products
Datasheet: Download MC12430FN datasheet File size : 119 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock Generator
The MC12430 is a general purpose synthesized clock source targeting applications that require both serial and parallel interfaces. Its internal VCO will operate over a range of frequencies from 400 to 800MHz. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4 or 8. With the output configured to divide the VCO frequency by 2, and with a 16.000MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1MHz steps. The PLL loop filter is fully integrated so that no external components are required.
MC12430
HIGH FREQUENCY PLL CLOCK GENERATOR
· · · · · · · · · ·
50 to 800MHz Differential PECL Outputs ±25ps PeaktoPeak Output Jitter Fully Integrated PhaseLocked Loop Minimal Frequency OverShoot Synthesized Architecture Serial 3Wire Interface Parallel Interface for PowerUp Quartz Crystal Interface 28Lead PLCC Package Operates from 3.3V or 5.0V Power Supply
FN SUFFIX 28LEAD PLCC PACKAGE CASE 77602
Functional Description The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 8 before being sent to the phase detector. With a 16MHz crystal, this provides a reference frequency of 2MHz. Although this data sheet illustrates functionality only for a 16MHz crystal, any crystal in the 1020MHz range can be used.
FA SUFFIX 32LEAD TQFP PACKAGE CASE 873A02
The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is applied to the phase detector. The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4 or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated in 50 to VCC 2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the phaselocked loop to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes valid. On the LOWtoHIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGHtoLOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information.
2/97
© Motorola, Inc. 1997
1
REV 1
MC12430
VCC 25 S_CLOCK S_DATA S_LOAD PLLVCC FREF_EXT XTAL_SEL XTAL1 26 27 28 1 2 3 4 5 XTAL2 6 7 8 9 M[1] 10 M[2] 11 M[3] FOUT 24 FOUT GND 23 22 VCC 21 TEST GND 20 19 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4]
32Lead Pinout TBD
28Lead Pinout (Top View)
15 14 13 12
N[1:0] 00 01 10 11 Input XTAL_SEL OE
Output Division 2 4 8 1 0 FREF_EXT Disabled 1 XTAL Enabled
OE P_LOAD M[0]
PIN DESCRIPTIONS
Pin Name Inputs XTAL1, XTAL2 S_LOAD (Int. Pulldown) S_DATA (Int. Pulldown) S_CLOCK (Int. Pulldown) P_LOAD (Int. Pullup) M[8:0] (Int. Pullup) N[1:0] (Int. Pullup) OE (Int. Pullup) Outputs FOUT, FOUT TEST Power VCC PLL_VCC GND Other FREF_EXT (Int. Pulldown) XTAL_SEL (Int. Pullup) LVCMOS/CMOS input which can be used as the PLL reference. LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input. This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through VCC 85mA. This is the positive supply for the PLL, and should be as noisefree as possible for lowjitter operation. This supply is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC 15mA. These pins are the negative supply for the chip and are normally all connected to ground. These differential positivereferenced ECL signals (PECL) are the output of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. The output is singleended ECL. These pins form an oscillator when connected to an external seriesresonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGHtoLOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOWtoHIGH transition of P_LOAD for proper operation. These pins are used to configure the PLL loop divider. They are sampled on the LOWtoHIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOWtoHIGH transition of P_LOAD. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. Function
MOTOROLA
2
TIMING SOLUTIONS BR1333 -- Rev 6
MC12430
MC12430 BLOCK DIAGRAM
+3.3 or 5.0V
2MHz FREF DIV 8 XTAL_SEL FREF_EXT 3 2 4 16MHz 5 OE 6 XTAL1 OSC XTAL2
PLL_VCC PHASE DETECTOR VCO 9BIT DIV M COUNTER DIV N (1, 2, 4, 8) VCC0 25 24 23 FOUT FOUT
+3.3 or 5.0V
400800 MHz
20 LATCH LATCH
TEST
S_LOAD P_LOAD
28 7 0 27 26 VCC1 21 8:16 9 +3.3 or 5.0V M[8:0] 17, 18 2 N[1:0] 22, 19 1 0 1 LATCH
S_DATA S_CLOCK
9BIT SR
2BIT SR
3BIT SR
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: FOUT = (FXTAL ÷ 8) x M ÷ N (1) The user can identify the proper M and N values for the desired frequency from the above equations. The four output frequency ranges established by N are 400800MHz, 200400MHz, 100200MHz and 50100MHz respectively. From these ranges the user will establish the value of N required, then the value of M can be calculated based on the appropriate equation above. For example if an output frequency of 131MHz was desired the following steps would be taken to identify the appropriate M and N values. 131MHz falls within the frequency range set by an N value of 4 so N [1:0] = 01. For N = 4 FOUT = M ÷ 2 and M = 2 x FOUT. Therefore M = 131 x 2 = 262, so M[8:0] = 100000110. Following this same procedure a user can generate any whole frequency desired between 50 and 800MHz. Note that for N > 2 fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies acheivable) will be equal to FXTAL ÷ 8 ÷ N. For input reference frequencies other than 16MHz the set of appropriate equations can be deduced from equation 1. For computer applications another useful frequency base would be 16.666MHz. From this reference one can generate a family of output frequencies at multiples of the 33.333MHz PCI clock. As an example to generate a 133.333MHz clock
Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 M 400 for any input reference. Assuming that a 16MHz reference frequency is used the above equation reduces to: FOUT = 2 x M ÷ N Substituting the four values for N (1, 2, 4, 8) yields: FOUT = 2M, FOUT = M, FOUT = M ÷ 2 and FOUT = M ÷ 4 for 200 < M < 400
TIMING SOLUTIONS BR1333 -- Rev 6
3
MOTOROLA
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