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Part: MC14560BCL
Category:
Description: NBCD Adder
Company: Motorola Semiconductor Products
Datasheet: Download MC14560BCL datasheet File size : 43 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14559B See Page 398
MC14560B NBCD Adder
The MC14560B adds two 4bit numbers in NBCD (natural binary coded decimal) format, resulting in sum and carry outputs in NBCD code. This device can also subtract when one set of inputs is complemented with a 9's Complementer (MC14561B). A ll inputs and outputs are active high. The carry input for the least significant digit is connected to VSS for no carry in. · Diode Protection on All Inputs · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Value Unit V V 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 ± 10 500 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) mA mW
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = 55° to 125°C for all packages.
_C _C
7 15 14 1 2 3 4 5 6
BLOCK DIAGRAM
Cin A1 B1 A2 B2 A3 B3 A4 B4 S1 S2 S3 S4 Cout 13 12 11 10 9
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
TRUTH TABLE*
Input A4 0 0 0 0 0 0 1 0 1 A3 0 0 1 1 1 1 0 1 0 A2 0 0 0 0 1 1 0 1 0 A1 0 0 0 0 1 1 0 0 1 B4 0 0 0 0 0 0 0 1 1 B3 0 0 0 0 1 1 1 0 0 B2 0 0 1 1 0 0 0 0 0 B1 0 0 1 1 0 0 1 0 1 Cin 0 1 0 1 0 1 0 0 1 Cout 0 0 0 0 1 1 1 1 1 S4 0 0 0 1 0 0 0 0 1 Output S3 0 0 1 0 0 0 0 1 0 S2 0 0 1 0 0 1 1 0 0 S1 0 1 1 0 1 0 1 0 1
VDD = PIN 16 VSS = PIN 8
* Partial truth table to show logic operation for representative input values.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3 0 1/94
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 1994
MC14560B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (1.68 µA/kHz) f + IDD IT = (3.35 µA/kHz) f + IDD IT = (5.03 µA/kHz) f + IDD µAdc # Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.005.
PIN ASSIGNMENT
A2 B2 A3 B3 A4 B4 Cin VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD A1 B1 S1 S2 S3 S4 Cout
MC14560B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns tTLH, tTHL Propagation Delay Time A or B to S tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 297 ns tPLH, tPHL = (0.5 ns/pF) CL + 195 ns A or B to Cout tPLH, tPHL = (1.7 ns/pF) CL + 565 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 145 ns Cin to Cout tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 187 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns TurnOff Delay Time Cin to S tPLH = (1.7 ns/pF) CL + 715 ns tPLH = (0.66 ns/pF) CL + 197 ns tPLH = (0.5 ns/pF) CL + 215 ns TurnOn Delay Time Cin to S tPHL = (1.7 ns/pF) CL + 565 ns tPHL = (0.66 ns/pF) CL + 197 ns tPHL = (0.5 ns/pF) CL + 145 ns tPLH 5.0 10 15 tPHL 5.0 10 15 -- -- -- 650 230 170 1800 600 450 -- -- -- 800 350 240 2250 975 750 ns tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- 750 330 220 650 230 170 550 220 160 2100 900 675 ns 1800 600 450 ns 1500 600 450 ns ns * The formulas given are for the typical characteristics only at 25_C. # Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 20 ns 90% 50% 10% 1 2f 20 ns VDD VSS ANY INPUT 20 ns 90% 50% 10% tPLH tPHL 20 ns VDD VSS ALL INPUTS VOH ANY OUTPUT VOL Duty Cycle = 50% All outputs connected to respective CL loads f = System clock frequency tTLH tTHL ANY OUTPUT 50% 10% 90% VOH VOL
Figure 1. Power Dissipation Waveforms
Figure 2. Switching Time Waveforms
MOTOROLA CMOS LOGIC DATA
MC14560B 3
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