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Part: MC14568BCL
Category:
Analog & Mixed-Signal Processing
Description: Phase Comparator And Programmable Counters
Company: Motorola Semiconductor Products
Datasheet: Download MC14568BCL datasheet File size : 135 kB
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Datasheet text preview:
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase Comparator and Programmable Counters
The MC14568B consists of a phase comparator, a divideby4, 16, 64 or 100 counter and a programmable dividebyN 4bit binary counter (all positiveedge triggered) constructed with MOS Pchannel and Nchannel enhancement mode devices (complementary MOS) in a monolithic structure. T h e MC14568B has been designed for use in conjunction with a programmable dividebyN counter for frequency synthesizers and phase locked loop applications requiring low power dissipation and/or high noise immunity. This device can be used with both counters cascaded and the output of the second counter connected to the phase comparator (CTL high), or used independently of the programmable dividebyN counter, for example cascaded with a MC14569B, MC14522B or MC14526B (CTL low). · Supply Voltage Range = 3.0 to 18 V · Capable of Driving Two LowPower TTL Loads, One LowPower Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range. · Chip Complexity: 549 FETs or 137 Equivalent Gates MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating Symbol VDD Vin Iin PD TA Tstg DC Supply Voltage Value
MC14568B
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unit Vdc Vdc 0.5 to + 18 ± 10 500 55 to + 125 65 to + 150 Input Voltage, All Inputs 0.5 to VDD + 0.5 DC Input Current, per Pin Power Dissipation, per Package Operating Temperature Range Storage Temperature Range mAdc mW
TA = 55° to 125°C for all packages.
TRUTH TABLE
F Pin 10 0 0 1 1 G Pin 11 0 1 0 1 Division Ratio of Counter D1 4 16 64 100
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
The divide by zero state on the programmable dividebyN 4bit binary counter, D2, is illegal.
BLOCK DIAGRAM
PCin 14 (REF.) B TG TG C1 9 COUNTER D1 10 F CTL 15 TG "0" 3 PE 2 DP3 4BIT PROGRAMMABLE COUNTER D2 DP0 1 Q1/C2 D2 "0" VDD = PIN 16 VSS = PIN 8
REV 3 1/94
A
PHASE COMPARATOR
13 PCout 12 LD
CTL HIGH
11 G PCin P/C C1 D1 C1 PCout LD PCin
CTL LOW
PCout P/C LD D1
"0" Q1/C2
D2 Q1/C2
4
5 6 DP2 DP1
7
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14568B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 1.2 0.25 0.62 1.8 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 1.0 0.2 0.5 1.5 0.51 1.3 3.4 -- -- -- -- -- 1.7 0.36 0.9 3.5 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 0.7 0.14 0.35 1.1 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage# "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) ThreeState Leakage Current Pins 1, 13 VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.2 µA/kHz) f + IDD IT = (0.4 µA/kHz) f + IDD IT = (0.9 µA/kHz) f + IDD µAdc ITL 15 -- ± 0.1 -- ± 0.0001 ± 0.1 -- ± 3.0 µAdc # Noise immunity for worst input combination. Noise Margin for both "1" and "0" level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 1 x 103 (CL 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. Pin 15 is connected to VSS or VDD for input voltage test.
PIN ASSIGNMENT
Q1/C2 PE "0" DP3 DP2 DP1 DP0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CTL PCin PCout LD G F C1
MC14568B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- 15 15 15 Typ 180 90 65 100 50 40 125 60 45 -- -- -- Max 360 180 130 200 100 80 250 120 90 -- -- -- Unit ns Output Rise Time Output Fall Time tTHL ns Minimum Pulse Width, C1, Q1/C2, or PCin Input tWH ns Maximum Clock Rise and Fall Time, C1, Q1/C2, or PCin Input PHASE COMPARATOR Input Resistance Input Sensitivity, dc Coupled TurnOff Delay Time, PCout and LD Outputs TurnOn Delay Time. PCout and LD Outputs DIVIDEBY4, 16, 64 OR 100 COUNTER (D1) Maximum Clock Pulse Frequency Division Ratio = 4, 64 or 100 fcl 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 3.0 8.0 10 1.0 3.0 50 -- -- -- -- -- -- 6.0 16 22 2.5 6.3 9.7 450 190 130 720 300 200 -- -- -- -- -- -- ns 900 380 260 1440 600 400 MHz Rin -- tPHL 5.0 to 15 5.0 to 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- 106 -- M tTLH, tTHL µs See Input Voltage 550 195 120 675 300 190 1100 390 240 1350 600 380 ns tPLH ns Division Ratio = 16 Propagation Delay Time, Q1/C2 Output Division Ratio = 4, 64 or 100 Division Ratio = 16 PROGRAMMABLE DIVIDEBYN 4BIT COUNTER (D2) Maximum Clock Pulse Frequency (Figure 3a) TurnOn Delay Time, "0" Output (Figure 3a) TurnOff Delay Time, "0" Output (Figure 3a) Minimum Preset Enable Pulse Width fcl 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 1.2 3.0 4.0 -- -- -- -- -- -- -- -- -- 1.8 8.5 12 450 190 130 225 85 60 75 40 30 -- -- -- 900 380 260 450 170 150 250 100 75 MHz tPLH ns tPHL ns tWH(PE) ns
MOTOROLA CMOS LOGIC DATA
MC14568B 3
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