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Part: MC14569BCL
Category:
Logic
Description: Programmable Divide-by-n Dual 4-bit Binary/bcd Down Counter
Company: Motorola Semiconductor Products
Datasheet: Download MC14569BCL datasheet File size : 291 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary or BCD down counter constructed with MOS Pchannel and Nchannel enhancement mode devices (complementary MOS) in a monolithic structure. T h i s device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. · Speedup Circuitry for Zero Detection · Each 4Bit Counter Can Divide Independently in BCD or Binary Mode · Can be Cascaded With MC14568B, MC14522B or MC14526B for Frequency Synthesizer Applications · All Outputs are Buffered · Schmitt Triggered Clock Conditioning MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Value Unit V V 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 ± 10 500 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) mA mW
TA = 55° to 125°C for all packages.
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
P0 P1 P2 P3 CTL = Low for Binary Count CTL = High for BCD Count 3 4 5 6 CTL1 CTL2 2 10 P4 P5 P6 P7 11 12 13 14 VDD = PIN 16 VSS = PIN 8 15
CLOCK
9
BINARY/BCD COUNTER #1
CLOCK LOAD
BINARY/BCD COUNTER #2
Q
CASCADE 7 FEEDBACK
ZERO DETECT ENCODER
1 ZERO DETECT
REV 3 1/94
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14569B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 Vin = 0 or VDD "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc Vdc "1" Level VOH 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 5.0 10 15 2.25 4.50 6.75 2.75 5.50 8.25 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Source VIL Vdc IOH mAdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.58 µA/kHz) f + IDD IT = (1.20 µA/kHz) f + IDD IT = (1.95 µA/kHz) f + IDD µAdc # Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14569B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tWH 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- 300 150 115 -- -- -- 380 150 100 530 225 155 100 45 30 3.5 9.5 13.0 NO LIMIT 600 300 200 1000 400 300 -- -- -- 2.1 5.1 7.8 ns All Types Typ # 100 50 40 100 50 40 420 175 125 675 285 200 Min -- -- -- -- -- -- -- -- -- -- -- -- Max 200 100 80 200 100 80 700 300 250 1200 500 400 ns Unit ns Output Rise Time Output Fall Time tTHL ns TurnOn Delay Time Zero Detect Output tPLH ns Q Output TurnOff Delay Time Zero Detect Output ns Q Output Clock Pulse Width ns Clock Pulse Frequency fcl MHz Clock Pulse Rise and Fall Time tTLH, tTHL µs # Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING WAVEFORMS
20 ns 20 ns CLOCK 10% 90% 50% tWH tPLH Q 10% 90% 50% tTLH tTHL tPHL fin = fmax
Figure 1.
20 ns 20 ns CLOCK 10% 90% 50% tWH tPLH 90% ZERO DETECT tTLH 10% tTHL tPHL
Figure 2. MOTOROLA CMOS LOGIC DATA MC14569B 3
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