Details, datasheet, quote on part number: MC33285DR2
CategoryAnalog & Mixed-Signal Processing => Power Pre-Drivers
TitlePower Pre-Drivers
DescriptionMC33285 Automotive Dual High Side Tmos Driver
CompanyMotorola Semiconductor Products
DatasheetDownload MC33285DR2 datasheet
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Features, Applications

Automotive Dual High Side TMOS Driver

The is a dual high side TMOS driver designed for use in the harsh automotive switching applications. The purpose of the is to drive two power n-channel FETs in a high side application with an inductive load. The application in an automotive environment requires the capability of withstanding high voltages and load dump transients. The MC33285 is able to withstand reverse battery conditions at selected pins. It protects the n-channel power FET on OUT1 under over current condition. This device has one input to control both stages on or off.Temperature Range from to +125° CPWM CapabilityPower TMOS # 1 Over-Current and Short-Circuit ProtectionVoltage Range to 40VExtended Temperature Range from to 125° CLoad Dump ProtectedOver Voltage Detection and Activation of OUT2 during OvervoltageSingle Input Control for both Output StagesCapacitor Value of 100nF Connected to Pin CPAnalog Input Control Measurement DetectionOUT1 LOAD leakage measurement detection

This document contains information on a new product under development. Motorola reserves the © Motorola,Inc 1999 right to change or discontinue this product without notice.

Rating Maximum voltage at pins OUT1 OUT2 Maximum voltage at pin CP Input voltage i at DRN Input voltage i at SRC Input voltage at pin VCC Input Voltage at pin IN. Condition -2V<VVCC <40V Operational voltage VVCC at pin VCC THERMAL RATINGS Rating Storage Temperature Operating ambient temperature Symbol T stg Ta Value to +125 Unit Symbol U T VCP VDRN VSRC VCC VIN VVCC Value VVCC -2 to VVCC to Vi Unit

ELECTRICAL CHARACTERISTICS. (T A from to +125°C, Vcc from to 20V, unless otherwise noted)

Load Dump Detection Time Load Dump Activation Time Error Voltage Threshold Overcurrent Detection Time tLDdet tOUT2act VDRN - VSRC tOCdet V µs

Leakage Current Leakage Current Detection Time ILCdet tLCdet mA µs
Operating Current (7V<VDRN <20V) Leakage current (0V<VDRN <20V, VVCC <4V) I DRN I leak_DRN mA µA

Output On Voltage. Charge Pump ON Turn off current, Vout >0.5V Turn On Time, 7V < Vcc < 10V, Vout 10V < Vcc < 20V, Vout > Vcc+11 Von Ioutoff ton µA ms

Supply Voltage Range Quiescent Supply Current at Vcc = 20V Vcc Icc V mA

Input Low Voltage OUT1 Input High Voltage OUT1 Input Hysteresis OUT1, OUT2 Input Pull Down Current, 0.7V<Vin<6V Open Input Voltage Input Low Voltage OUT2 Input High Voltage OUT2 Vil Vih Vhys Iin Viop µA V

Turn On Characteristics The power FETs are turned on by charging their gate capacities with a current flowing out of pin OUT1 and OUT2. During PWM, the values of table below are guaranteed. They are measured with on OUT1 and OUT2. - test condition IN : ramp to 5V.

Table 1 Turn on behaviour Voltage V VCC < V VCC < V VCC < V VCC < 40V Minimum V OUT1,OUT2 after = 100µsec VVCC - 0.7V VVCC - 0.7V VVCC - 0.7V Minimum V OUT1,OUT2 after = 1.0msec VVCC + 5.95V VVCC + 9.35V Minimum V OUT1,OUT2 after = 1.5msec VVCC + 7V VVCC + 11V

The output voltages at OUT1 and OUT2 are limited by controlling the current sources on2 to avoid currrent flowing through the external or the internal zener diode. If Vcc + Vth (threshold voltage) is reached , the current sources are turned off. - threshold V TH1 for OUT1 output voltage control Vz - threshold VTH2 for OUT2 output voltage control < 15V Turn off characteristics The power FETs on OUT1 and OUT2 are turned off by discharging the gate capacity with the constant discharge current I OUToff. - discharge current I OUTxoff : IOUTxoff = 110µA condition : V OUTx IN < VTHRxIN ) Test conditions for switching off the power FETs 1. IN open - 2. Stages disabled via pin - 3. Stage OUT1 disabled by an over current error


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