|Description||Lithium Battery Protection Circuit For One Cell Smart Battery Packs|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC33349N-1 datasheet
LITHIUM BATTERY PROTECTION CIRCUIT FOR ONE CELL SMART BATTERY PACKS
Lithium Battery Protection Circuit for One Cell Battery Packs
The is a monolithic lithium battery protection circuit that is designed to enhance the useful operating life of a one cell rechargeable battery pack. Cell protection features consist of internally trimmed charge and discharge voltage limits, charge and discharge current limit detection, and a virtually zero current sleepmode state when the cell is discharged. This protection circuit requires a minimum number of external components and is targeted for inclusion within the battery pack. This MC33349 is available in the SOT23 6 lead surface mount package. Internally Trimmed Charge and Discharge Voltage Limits
Charge and Discharge Current Limit Detection Virtually Zero Current Sleepmode State when Cells are Discharged Dedicated for One Cell Applications Minimum Components for Inclusion within the Battery Pack Available in a Low Profile Surface Mount Package
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc. 1998 Rev 0
Charge Overvoltage Threshold (V) MC33349N9 MC33349N10 Charge Overvoltage Hysteresis (mV) Discharge Undervoltage Threshold (V) Current Limit Threshold (mV) to 85°C SOT 23 SOT23 Operating Temperature Range
Thermal Resistance, JunctiontoAir N Suffix, SOT23 Plastic Package, Case 1262 Operating Junction Temperature (Note 1) Storage Temperature RJA TJ °C/W °C TBD to 85 Tstg to 125
Input Voltage Discharge Gate Drive Output (Pin 1) to Gnd (Pin 6) Charge Gate Drive Common/Current Limit (Pin to V cell (Pin 5) Charge Gate Drive Output (Pin 3) to Vcell (Pin 5) Overvoltage Delay Capacitor (Pin 4) to Gnd (Pin 6) Cell Voltage (Pin 5) to Gnd (Pin 6)
ELECTRICAL CHARACTERISTICS (Ct = 0.01 µF, = 25°C, for min/max values TA is the operating junction temperature range
VOLTAGE SENSING Cell Charging Cutoff (Pin 5 to Pin 6) Overvoltage Threshold, VCell Increasing 1, 3 Suffix 2, 4 Suffix Overvoltage Hysteresis VCell Decreasing Vth(OV) mV V Cell Discharging Cutoff (Pin 5 to Pin 6) Undervoltage Threshold, VCell Decreasing 1, 3 Suffix 2, 4 Suffix Vth(UV) Input Bias Current During Cell Voltage Sample (Pin 5) Overvoltage Delay Time (Vcell 4.5 V) Unervoltage Delay Time (Vcell 2.1 V) Cell Voltage Sampling Period IIIB µA t(ovd) t(uvd) ms t(smpl) t(rep) 2.0 26 Cell Voltage Sampling Repitition Period CURRENT SENSING Discharge/Charge Current Limit (Pin 2 to Pin 6) Discharge Threshold Voltage 1, 2 Suffix 3, 4 Suffix Discharge Current Hysteresis Charge Threshold Voltage 1. 2 Suffix 3, 4 Suffix Charge Current Hysteresis Vth(dschg) mV DCH Vth(chg) mV CCH t(ccld) t(dcld) Volc µs Current Limit Delay Time (1.0 nF load CO & DO; to VDD/2) Charge Gate Drive Output (Pin 3) Discharge Gate Drive Output (Pin 1) Charge Gate Drive Output Low (Pin 3 to Pin = 50 µA)
OUTPUTS Charge Gate Drive Output High (Pin 5 to Pin = 50 µA) Vohc Vold Discharge Gate Drive Output Low (Pin 1 to Pin = 50 µA) Discharge Gate Drive Output High (Pin 5 to Pin = 50 µA) Vohd TOTAL DEVICE Average Cell Current Operating (Vcell 3.9 V) Sleepmode (Vcell 2.0 V) Icell nA V Minimum Operating Cell Voltage Vcell
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