|Category||Analog & Mixed-Signal Processing => Switches & Multiplexers => Power High Side Switches|
|Title||Power High Side Switches|
|Description||MC33888FB Quad High Side And Octal Low Side Switch For Automotive|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC33888FB datasheet
Quad High Side and Octal Low Side Switch for Automotive
This QHSOLSS is a single packaged combination of four discrete high-side FETs and an integrated IC consisting of eight low-side drivers with appropriate control, protection, and diagnostic features. The high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. The low-side drivers are capable of controlling low current on/off type inductive loads, such as relays and solenoids as well as LED indicators and small lamps. The device will be useful in body control, instrumentation, and other high power switching applications and systems. Operating Voltage Range from to 27V Maximum Breakdown Voltage greater than 41V Protected in case of loss of ground, loss of Vbat Enhanced -16V Reverse Battery Protection (MOSFETs turned ON) Surface Mount Power Package Dual 10m High Side, Dual 40m High Side, Octal 500m Low Side Configurable SPI and/Or Direct High Side Control SPI Low Side Control with Single Configurable Direct Input SPI or Direct Fed Watchdog SPI Diagnostics Individual Overtemperature Protection with Hysteresis Configurable Open Load Detection in Off-State Short-Circuit Protection to ground and to Vbat. Configurable High Side Current Sense Configurable High Side Current limitation Under and Over Voltage Protection Standby Current less than at Vbat<14V and Tj<85°C.
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Description Ground. These pins serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. Battery Voltage Each pin is the source a 10m Ohm FET, high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During failsafe mode, output HS0 will be turned on until the device is reinitialized and then immediately followed by normal operation. Each pin is the source a 40m Ohm FET, high-side driver which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During failsafe mode, output HS2 will be turned on until the device is reinitialized and then immediately followed by normal operation. Each High-Side Input pin is used to directly control only one designated HSO output. These inputs may or may not be activated depending upon the configured state of the internal logic. The Current Sense pins deliver a ratioed amount of the high-side output currents that can be used to generate signal ground referenced output voltages for use by the microcontroller. Each respective CSNS pin can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or HS3 are sensed via CSNS2-3. Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through the connected loads. Each of the outputs are actively clamped at 53V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500mA. Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through the connected loads. Each of the outputs are actively clamped at 53V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800mA The low-side input pin is used to directly control a number of the low-side devices as configured by SPI. This pin may or may not be activated depending upon the configured state of the internal logic. The Serial Clock Pin is connected to the SCLK pin of the master device which is a bit (shift) clock for the SPI port. It transitions 1 time per bit transferred at an operating frequency, fSPI and is idle between command transfers. is 50% duty cycle, and has CMOS logic levels. This signal is used to shift data to and from the device.. The Serial Input is connected to the SPI Serial Data Output pin of the master device from which it receives output command data. This input has an internal active pulldown and requires CMOS logic levels. The serial data transmitted on this line a 16 bit control command sent MSB first, which controls the twelve output channels. Bits D0-D3 control the high-side outputs HS0-HS3, respectively. Bits D4-D11 control the low-side outputs LS4-LS11, respectively. The master will ensure that data is available on the falling edge of SCLK.
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