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Part: MC68307V
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Company: Motorola Semiconductor Products
Datasheet: Download MC68307V datasheet File size : 32 kB
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MOTOROLA
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SEMICONDUCTOR
TECHNICAL INFORMATION
MC68307 MC68307V
Technical Summary
Integrated Multiple-Bus Processor
The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V, static operation in a small package, the MC68307 delivers cost-effective performance to handheld, batterypowered applications. The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus, 8051 bus, and Motorola bus (M-bus) or I2C bus1. The dynamically sized 68000 bus allows 16-bit performance out of static random access memory (SRAM) while still providing a low-cost interface to an 8-bit read-only memory (ROM). The 8051 bus interfaces gluelessly to 8051-type devices and allows the reuse of applicationspecific integrated circuits (ASICs) designed for this industry standard bus. The M-bus is an industry standard 2-wire interface which provides efficient communications with peripherals such as EEPROM, analog/digital (A/ D) converters, and liquid crystal display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM, SRAM, 8051 devices, M-bus devices, and memory-mapped peripherals. The MC68307 also incorporates a slave mode which allows the EC000 core to be turned off, providing a 3.3-V static, low-power multi-function peripheral for higher performance M68000 family processors.
SYSTEM INTEGRATION MODULE (SIM07) 8/16-BIT M68000 BUS INTERFACE 8051 BUS INTERFACE CHIP SELECT AND DTACK INTERRUPT CONTROLLER PROCESSOR CONTROL, CLOCK AND LOW POWER SYSTEM PROTECTION PARALLEL I/O PORTS JTAG PORT DUAL TIMER MODULE STATIC EC000 CORE PROCESSOR
DYNAMIC BUS SIZING EXTENSION
68000 INTERNAL BUS
M-BUS MODULE
UART SERIAL I/O
Figure 1. MC68307 Block Diagram
1. I2C
bus is a proprietary Philips interface bus.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© MOTOROLA, 1993
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The main features of the MC68307 include: · Static EC000 Core Processor--Identical to MC68EC000 Microprocessor -- Full compatibility with MC68000 and MC68EC000 -- 24-bit address bus, for 16-Mbyte off-chip address space -- 16-bit on-chip data bus for MC68000 bus operations -- Static design allows processor clock to be stopped providing dramatic power savings -- 2.4 MIPS performance at 16.67-MHz processor clock · External M68000 Bus Interface with Dynamic Bus Sizing for 8-bit and 16-bit Data Ports · External 8-Bit Data Bus Interface (8051-Compatible) · M-Bus Module -- Provides interchip bus interface for EEPROMs, LCD controllers, A/D converters, etc. -- Compatible with industry-standard I2C bus -- Master or slave operation modes, supports multiple masters -- Automatic interrupt generation with programmable level -- Software-programmable clock frequency -- Data rates from 4100 Kbit/s above 3.0-MHz system clock · Universal Asynchronous Receiver/Transmitter (UART) Module -- Flexible baud rate generator -- Based on MC68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) programming model -- 5 Mbits/s maximum transfer rate at 16.67-MHz system clock -- Automatic interrupt generation with programmable level -- Modem control signals available (CTS,RTS) · Timer Module -- Dual channel 16-bit general purpose counter/timer -- Multimode operation, independent capture/compare registers -- Automatic interrupt generation with programmable level -- Third 16-bit timer configured as a software watchdog -- 60-ns resolution at 16.67-MHz system clock -- Each timer has an input and an output pin · System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External Programmable Array Logic (PALs), Transistor-Transistor Logic (TTL), and ASICs, such as: -- System configuration, programmable address mapping -- System protection by hardware watchdog logic -- Power-down mode control, programmable processor clock driver -- Four programmable chip selects with wait state generation logic -- Three simple peripheral chip selects -- Parallel input/output ports, some with interrupt capability -- Programmed interrupt vector response for on-chip peripheral modules -- IEEE 1149.1 boundary scan test access port (JTAG) · Operation from DC to 16.67 MHz (Processor Clock) · Operating Voltages of 3.3V ± 0.3V and 5V ± 0.5V · Compact 100-Lead Quad Flat Pack (QFP) Package
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MC68307 TECHNICAL INFORMATION
MOTOROLA
M68300 FAMILY
The MC68307 is one of a series of components in Motorola's M68300 family. Other members of the family include the MC68302, MC68306, MC68330, MC68331, MC68332, MC68F333, MC68334, MC68340, MC68341, MC68349, and MC68360.
ORGANIZATION
The M68300 family of integrated processors and controllers is built on an M68000 core processor and a selection of intelligent peripherals appropriate for a set of applications. Common system glue logic such as address decoding, wait state insertion, interrupt prioritization, and watchdog timing is also included. Each member of the M68300 family is distinguished by its selection of on-chip peripherals. Peripherals are chosen to address specific applications but are often useful in a wide variety of applications. The peripherals may be highly sophisticated timing or protocol engines that have their own processors, or they may be more traditional peripheral functions, such as UARTs and timers.
ADVANTAGES
By incorporating so many major features into a single M68300 family chip, a system designer can realize significant savings in design time, power consumption, cost, board space, pin count, and programming. The equivalent functionality can easily require 20 separate components. Each component might have 1664 pins, totaling over 350 connections. Most of these connections require interconnects or are duplications. Each connection is a candidate for a bad solder joint or misrouted trace. Each component is another part to qualify, purchase, inventory, and maintain. Each component requires a share of the printed circuit board. Each component draws power, which is often used to drive large buffers to get the signal to another chip. The cumulative power consumption of all the components must be available from the power supply. The signals between the central processing unit (CPU) and a peripheral might not be compatible nor run from the same clock, requiring time delays or other special design considerations. In an M68300 family component, the major functions and glue logic are all properly connected internally, timed with the same clock, fully tested, and uniformly documented. Only essential signals are brought out to pins. The primary package is the surface-mount plastic QFP for the smallest possible footprint.
MOTOROLA
MC68307 TECHNICAL INFORMATION
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