Details, datasheet, quote on part number: MC74HC165AJ
PartMC74HC165AJ
Category
Description
CompanyMotorola Semiconductor Products
DatasheetDownload MC74HC165AJ datasheet
  

 

Features, Applications

The MC54/74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device an 8­bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2­input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates LOGIC DIAGRAM

A B PARALLEL DATA INPUTS C QH SERIAL DATA OUTPUTS
D SUFFIX SOIC PACKAGE CASE 751B­05 DT SUFFIX TSSOP PACKAGE CASE 948F­01
ORDERING INFORMATION MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP
SERIAL SHIFT/ PARALLEL LOAD CLOCK F G PIN 16 = VCC PIN 8 = GND H QH GND VCC CLOCK INHIBIT SA QH
H 6 SERIAL SA 10 DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 CLOCK INHIBIT 15

Serial Shift/ Parallel Load don't care Inputs Clock Inhibit Clock Internal Stages SA A­H a...h QB b QAn No Change No Change Output QH h QGn Operation Asynchronous Parallel Load Serial Shift via Clock Serial Shift via Clock Inhibit Inhibited Clock No Clock

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 10/95

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package Storage Temperature mW Tstg 65 to

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP)

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C Ceramic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).


Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 125_C 0.1 Unit V Maximum Low­Level Output Voltage Vin = VIH or VIL |Iout| µA 0.1 Vin = VIH or VIL |Iout| Vin = VCC or GND Vin = VCC or GND Iout 5.2 mA Iin Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) µA ICC NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8)
Maximum Propagation Delay, Clock (or Clock Inhibit) or QH (Figures 1 and 8)
Maximum Propagation Delay, Serial Shift/Parallel Load or QH (Figures 2 and 8)
Maximum Output Transition Time, Any Output (Figures 1 and 8)

NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Package)* 40

* Used to determine the no­load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).


 

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