Details, datasheet, quote on part number: MC74HC20D
PartMC74HC20D
CategoryLogic => Gates
DescriptionDual 4-input NAND Gate
CompanyMotorola Semiconductor Products
DatasheetDownload MC74HC20D datasheet
Cross ref.Similar parts: SN74HC20D
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Features, Applications

The MC74HC20A is identical in pinout to the LS20. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 28 FETs or 7 Equivalent Gates LOGIC DIAGRAM

This document contains information on a new product. Specifications and information herein are subject to change without notice. 1/98

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC


Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 125_C 0.1 Unit V Maximum Low­Level Output Voltage Vin = VIH |Iout| µA 0.1 Vin = VIH or VIL |Iout| Vin = VCC or GND Vin = VCC or GND Iout 5.2 mA Iin Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) µA ICC NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Maximum Propagation Delay, Input C to Output Y (Figures 1 and 2)
Maximum Output Transition Time, Any Output (Figures 1 and 2)

NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Di (P Power Dissipation Capacitance (Per G Gate)* 26

* Used to determine the no­load dynamic power consumption: CC V CC. For load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). tf INPUT OR D OUTPUT 10% tr TEST POINT VCC GND tPLH 50% 10% tTHL tPHL DEVICE UNDER TEST OUTPUT CL*


 

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