|Category||Logic => Parity Generators/Checkers|
|Description||9-bit Odd/even Parity Generator/checker|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC280D datasheet
|Cross ref.||Similar parts: CD74HC280M96, CD54HC147, CD54HC280, CD54HC283, CD54HC688, CD54HCT280, CD54HCT283, CD54HCT85, CD74HC147, CD74HC283|
The MC74HC280 is identical in pinout to the LS280. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This circuit consists of 9 databit inputs (A through I) and 2 outputs (Even Parity and Odd Parity) to allow both odd and even parity applications. Words greater than 9bits can be accommodated by cascading other HC280 devices. This device can be used in systems utilizing the LS180 parity generator/ checker. Although the HC280 does not have expander inputs, the corresponding function is provided by an input at pin 4 and the absence of any connection at pin 3. This permits the to be substituted for the LS180 to produce a similar function, even if the HC280s are mixed with existing LS180s. NOTE: Pullup resistors must be used on the LS180 outputs to interface with the HC280. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 226 FETs or 56.5 Equivalent Gates LOGIC DIAGRAM
= NO CONNECTION C 9BIT DATA WORD INPUTS VCC = PIN 14 GND = PIN 7 NO CONNECTION = PIN 5 6 EVEN PARITY ODD PARITY OUTPUTSOutputs Number of Inputs A through I That are High Even Parity H L Odd Parity L H
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit 85_C Symbol tPLH, tPHL tTLH, tTHL Cin Parameter VCC 25_C 125_C Unit ns Maximum Propagation Delay, Data Inputs to Parity Outputs (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance ns pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Package)* pF * Used to determine the noload dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
INPUTS H, I (Pins Ninebit dataword inputs. The data word placed on these pins is checked for even or odd parity. OUTPUTS Even Parity (Pin 5) Evenparity output. This pin goes high if the data word has even parity and low if the data word has odd parity. Odd Parity (Pin 6) Oddparity output. This pin goes high if the data word has odd parity and low if the data word has even parity.
TEST POINT tr DATA INPUT tPLH PARITY OUTPUT 50% 10% tTLH tTHL * Includes all probe and jig capacitance 50% 10% tPHL tf VCC GND DEVICE UNDER TEST OUTPUT CL*
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