Details, datasheet, quote on part number: MC74HC299N
PartMC74HC299N
CategoryLogic => Registers => Shift Registers
Description8-bit Bidirectional Universal Shift Register With Parallel I/o
CompanyMotorola Semiconductor Products
DatasheetDownload MC74HC299N datasheet
Cross ref.Similar parts: 5962-8780601RA
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Features, Applications

8-Bit Bidirectional Universal Shift Register with Parallel I/O

The MC74HC299 is identical in pinout to the LS299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC299 features a multiplexed parallel input/output data port to achieve full 8­bit handling a 20 pin package. Due to the large output drive capability and the 3­state feature, this device is ideally suited for interface with bus lines in a bus­oriented system. Two Mode­Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode­Select lines, S1 and S2, high. This places the outputs in the high­impedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active­low asynchronous Reset overrides all other inputs. Output Drive Capability: 15 LSTTL Loads for QA through QH 10 LSTTL Loads for QA and QH Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 398 FETs or 99.5 Equivalent Gates

SA (SHIFT RIGHT) 11 SH (SHIFT LEFT) 18 CLOCK 12 RESET MODE S1 SELECT S2 OUTPUT OE1 ENABLES OE2
PA/QA PB/QB PC/QC PD/QD PE/QE PF/QF PG/QG PH/QH QA QH

Symbol VCC Vin Vout Iin Iout ICC PD Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg 150 260

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)

Symbol Parameter VCC Vin, Vout TA tr, tf Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure VCC

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

Test Conditions Vout V or VCC 0.1 V |Iout| 20 µA Vout V or VCC 0.1 V |Iout| 20 µA

Maximum Input Leakage Current Maximum Three­State Leakage Current (QA thru QH) Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND µA Iout 0 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). ICC

Guaranteed Limit 85_C Symbol fmax Parameter VCC 17 20 Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and MHz tPLH, tPHL tPLH, tPHL Maximum Propagation Delay, Clock or QH (Figures 1 and ns Maximum Propagation Delay, Clock to QA thru QH (Figures 1 and 5) Maximum Propagation Delay, Reset or QH (Figures 2 and 5) ns tPHL Maximum Propagation Delay, Reset to QA thru QH (Figures 2 and 5) ns tPLZ, tPHZ tPZL, tPZH Maximum Propagation Delay, to QA thru QH (Figures 3 and 6) Maximum Propagation Delay, to QA thru QH (Figures 3 and 6) Maximum Output Transition Time, QA thru QH (Figures 1 and 5) Maximum Output Transition Time, or QH (Figures 1 and 5) Maximum Input Capacitance ns tTLH, tTHL tTLH, tTHL Cin ns pF Cout Maximum Three­State Output Capacitance (Output in High­Impedance State), QA thru QH NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Package)*, Outputs Enabled pF * Used to determine the no­load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).


 

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