|Category||Logic => Gates|
|Description||8-input NAND Gate|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC30D datasheet
The MC74HC30 is identical in pinout to the LS30. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 32 FETs or 8 Equivalent GatesInputs A through H All inputs H One or more inputs L Output L H
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit 85_C Symbol tPLH, tPHL tTLH, tTHL Cin Parameter VCC 25_C 125_C Unit ns Maximum Propagation Delay, Any Input to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance ns pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Gate)* pF * Used to determine the noload dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).TEST POINT OUTPUT DEVICE UNDER TEST CL*
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