|Category||Logic => Buffers/Inverters => 3-State|
|Description||8-input Data Selector/multiplexer With Data And Address Latches And 3-state Outputs|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC354 datasheet
8-Input Data Selector/ Multiplexer With Data and Address Latches and 3-State Outputs
The MC54/74HC354 is identical in pinout to the LS354. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC354 selects one of eight latched binary Data Inputs, as determined by the Address Inputs. The information at the Data Inputs is stored in the transparent 8bit Data Latch when the DataLatch Enable pin is held high. The Address information may be stored in the transparent Address Latch, which is enabled by the activehigh AddressEnable pin. The device outputs are placed in highimpedance states when Output Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low. The HC354 has a clocked Data Latch that is not transparent.
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: to 6V Low Input Current: 1µA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 326 FETs or 81.5 Equivalent Gates LOGIC DIAGRAMDATALATCH 9 ENABLE A0 ADDRESS INPUTS 12 A2 ADDRESS LATCH (TRANS PARENT) PIN 20 = VCC PIN 10 = GND
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature Range mW Tstg 65 to
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package Ceramic DIP
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) VCC
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C Ceramic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Symbol VIH Parameter Minimum HighLevel Input Voltage Condition Vout 0.1V or VCC 0.1V |Iout| 20µA Vout 0.1V or VCC 0.1V |Iout| 20µA Vin = VIH or VIL |Iout| 20µA Vin =VIH or VIL VOL Maximum LowLevel Output Voltage Vin = VIH or VIL |Iout| 20µA Vin = VIH or VIL Iin Maximum Input Leakage Current Vin = VCC or GND |Iout| 6.0mA |Iout| 7.8mA |Iout| 6.0mA |Iout| 7.8mA VCC V Guaranteed Limit µA V Unit V
Symbol IOZ Parameter Maximum ThreeState Leakage Current Maximum Quiescent Supply Current (per Package) Condition Output in HighImpedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0µA VCC V 6.0 Guaranteed Limit 125°C ±10.0 Unit µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Parameter Maximum Propagation Delay, or Y (Figures 2 and 6) Maximum Propagation Delay, DataLatch Enable or Y (Figures 3 and 6) Maximum Propagation Delay, or Y (Figures 2 and 6) Maximum Propagation Delay, AddressLatch Enable or Y (Figures 3 and 6) Maximum Propagation Delay, or Y (Figures 4 and 7) Maximum Propagation Delay, or Y (Figures 4 and 7) Maximum Output Transition Time, Any Output (Figures 1 and 6) Maximum Input Capacitance Maximum ThreeState Output Capacitance (Output in High Impedance State) VCC V Guaranteed Limit 85°C 125°C Unit ns
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Package)* pF * Used to determine the noload dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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