Details, datasheet, quote on part number: MC74HC366ADT
PartMC74HC366ADT
CategoryLogic
DescriptionHex 3-state Inverting Buffer With Common Enables
CompanyMotorola Semiconductor Products
DatasheetDownload MC74HC366ADT datasheet
Cross ref.Similar parts: 74AC16244, 74ACT16373, 74ACT16374, 74ACT16541, 74ACT16543, CD40109B, CD40109B-MIL, CD40109B-Q1, CD4502B, CD4502B-MIL
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Features, Applications

The MC54/74HC366 is identical in pinout to the LS366. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is a high­speed hex buffer with 3­state outputs and two common active­low Output Enables. When either of the enables is high, the buffer outputs are placed into high­impedance states. The HC366 has inverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 78 FETs or 19.5 Equivalent Gates

OUTPUT ENABLE 6 Y2 GND 12 A5 OUTPUT ENABLE VCC OUTPUT ENABLE A3 Y3

Symbol VCC Vin Iin Vout Iout PD TL Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP mW Tstg 65 to

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP) (Ceramic DIP)

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Symbol VCC TA Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C Ceramic DIP: ­ 10 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).


Maximum Input Leakage Current Maximum Three­State Leakage Current Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND µA Iout 0 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). ICC

Guaranteed Limit 85_C Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Parameter VCC 16 125_C Unit ns Maximum Propagation Delay, Input A to Output Y (Figures 1 and Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance ns tTLH, tTHL Cin ns pF Cout Maximum Three­State Output Capacitance (Output in High­Impedance State) NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* pF * Used to determine the no­load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

VCC tf 90% INPUT 50% 10% tPLH OUTPUT Y tTLH 50% 10% tTHL tPHL tr VCC GND OUTPUT Y OUTPUT ENABLE 50% GND tPZL 50% tPZH OUTPUT Y 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE

TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.


 

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