|Description||Hex 3-state Inverting Buffer With Separate 2-bit And 4-bit Sections|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC368AD datasheet
|Cross ref.||Similar parts: CD74HC368M, SN74HC368D, 74AC16244, 74ACT16373, 74ACT16374, 74ACT16541, 74ACT16543, CD40109B, CD40109B-MIL, CD40109B-Q1|
N SUFFIX PLASTIC PACKAGE 16LEAD CASE 64808 D SUFFIX SOIC PACKAGE 16LEAD CASE 751B05 DT SUFFIX TSSOP PACKAGE 16LEAD CASE 948F01 ORDERING INFORMATION MC74HCXXXAD MC74HCXXXADT Plastic SOIC TSSOP
The MC74HC368A is identical in pinout to the LS368. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is arranged into 2bit and 4bit sections, each having its own activelow Output Enable. When either of the enables is high, the affected buffer outputs are placed into highimpedance states. The HC368A has inverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 80 FETs or 20 Equivalent Gates
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1/97
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C TSSOP Package: 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC
Guaranteed Limit 85_C Symbol IOZ Parameter Test Conditions VCC 0.5 125_C Unit µA Maximum ThreeState Leakage Current Output in HighImpedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout 0 µA ICC Maximum Quiescent Supply Current (per Package) µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).b l Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH
Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3)
Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input CapacitanceMaximum ThreeState Output Capacitance (Output in HighImpedance State
NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD P Power Dissipation i C Capacitance i (P (Per B Buffer)* ff 40
* Used to determine the noload dynamic power consumption: CC V CC. For load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
VCC tr INPUT A tPHL OUTPUT Y tTHL 50% 10% tTLH 50% 10% tPLH tf VCC GND OUTPUT Y OUTPUT ENABLE 50% GND tPZL 50% tPZH OUTPUT Y 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
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