|Description||Octal 3-state Non-inverting Transparent Latch|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC373ASD datasheet
|Cross ref.||Similar parts: SN74HC373DBR, 74AC16244, 74ACT16373, 74ACT16374, 74ACT16541, 74ACT16543, CD40109B, CD40109B-MIL, CD40109B-Q1, CD4502B|
The MC54/74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled. The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC373A is the noninverting version of the HC533A. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 186 FETs or 46.5 Equivalent Gates LOGIC DIAGRAM
N SUFFIX PLASTIC PACKAGE CASE 73803 DW SUFFIX SOIC PACKAGE CASE 751D04 SD SUFFIX SSOP PACKAGE CASE 940C03 DT SUFFIX TSSOP PACKAGE CASE 948E02
ORDERING INFORMATION MC54HCXXXAJ Ceramic MC74HCXXXAN Plastic MC74HCXXXADW SOIC MC74HCXXXASD SSOP MC74HCXXXADT TSSOPOUTPUT ENABLE Q6 Q7 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS D3 Q3 GND VCC D4 Q4 LATCH ENABLE
LATCH ENABLE 11 1 Design Criteria Value 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product 0.0075 * Equivalent to a twoinput NAND gate. 1Inputs Output Enable Latch Enable Output L No Change Z
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package SSOP or TSSOP Package Storage Temperature mW Tstg 65 to
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) (Ceramic DIP)
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C Ceramic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C SSOP or TSSOP Package: 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 0.1 125_C Unit V Maximum LowLevel Output Voltage Vout V or VCC 0.1 V |Iout| µA 0.1 Vin = VIH or VIL |Iout| 6.0 mA |Iout| 7.8 mA Iin Maximum Input Leakage Current Maximum ThreeState Leakage Current Vin = VCC or GND µA IOZ Output in HighImpedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND |Iout| 0 µA ICC Maximum Quiescent Supply Current (per Package) µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5)
tPLZ tPHZ tPZL tPZH tTLH tTHL Cin
Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input CapacitanceMaximum ThreeState Output Capacitance (Output in HighImpedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the noload dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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