|Description||Analog Multiplexers/demultiplexers With Address Latch|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MC74HC4351DW datasheet
Analog Multiplexers/ Demultiplexers with Address Latch
The MC74HC4351A utilizes silicongate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The ChannelSelect inputs determine which one of the Analog Inputs/ Outputs to be connected, by means of an analog switch, to the Common Output/Input. The data at the ChannelSelect inputs may be latched by using the activelow Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The ChannelSelect and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so the ON resistance (Ron) is more linear over input voltage than Ron of metalgate CMOS analog switches. For multiplexers/demultiplexers without latches, see the HC4051A, HC4052A, and HC4053A. Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC VEE) 12.0 V Digital (Control) Power Supply Range (VCC GND) 6.0 V Improved Linearity and Lower ON Resistance than MetalGate Types Low Noise In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 222 FETs or 55.5 Equivalent Gates
This document contains information on a new product. Specifications and information herein are subject to change without notice.LOGIC DIAGRAM MC74HC4351A SinglePole, 8Position Plus Common Off and Address Latch
MULTIPLEXER/ DEMULTIPLEXER 4 X COMMON OUTPUT/INPUT Control Inputs Enable 2 C Select A ON Channel (LE = H)*LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2
No e None X = don't care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states.
Symbol VCC VEE VIS Vin I PD Parameter Value Unit Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) + 0.5 VEE 0.5 to VCC Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage DC Input Voltage (Ref. to GND) 0.5 to VCC 0.5 DC Current Into or Out of Any Pin mA Power Dissipation in Still Air, Plastic DIP SOIC or TSSOP Package Storage Temperature mW Tstg 150 260Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the ranges indicated in the Recommended Operating Conditions. Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. See Applications Information.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C TSSOP Package: 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Symbol VCC VEE VIS Vin Parameter Positive DC Supply Voltage Min 2.0 Max Unit (Ref. to GND) (Ref. to VEE) 6.0 12.0 Negative DC Supply Voltage Analog Input Voltage (Ref. to GND) 6.0 VEE GND VCC 1.2 Digital Input Voltage (Ref. to GND) GND VIO* TA Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types Input Rise and Fall Time, Channel Select or Enable Inputs (Figure 9a)
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit 85_C VCC b l Symbol VIH P Parameter T Test C Conditions U i Unit V Minimum HighLevel Input Voltage, ChannelSelect or Enable Inputs Maximum LowLevel Input Voltage, ChannelSelect or Enable Inputs Ron = Per Spec VIL Ron = Per Spec V Iin Maximum Input Leakage Current, ChannelSelect or Enable Inputs Vin = VCC or GND, VEE V µA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND Enables = VCC or GND VIS = VCC or GND VEE = GND VIO 0 V VEE 6.0 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
* For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
Guaranteed Limit b l Symbol Ron P Parameter T Test C Conditions di i VCC V VEE U i Unit Maximum "ON" Resistance Vin = VIL or VIH VIS = VCC to VEE 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = VCC or VEE (Endpoints) 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC VEE) 2.0 mA Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package
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