|Description||PCI Bridge/memory Controller|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MPC106 datasheet
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCTM microprocessor common hardware reference platform (CHRPTM) compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect (PCI) bus. In this document, the term `106' is used as an abbreviation for the phrase `MPC106 PCI bridge/memory controller.' This document contains pertinent physical characteristics of the 106. For functional characteristics, refer to the MPC106 PCI Bridge/Memory Controller User's Manual. This document contains the following topics:
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Document Revision History" Section 1.10, "Ordering Information"
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2001. All rights reserved.
In this document, the term `60x' is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601TM, PowerPC 603TM, or PowerPC 604TM microprocessors. Note that this does not include the PowerPC 602TM microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture it is specified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision). To locate any published errata or updates for this document, refer to the website at http://www.mot.com/SPS/PowerPC/.
The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus, and main memory. This section provides a block diagram showing the major functional units of the 106 and describes briefly how those units interact. Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than how these features are physically implemented on the device.Features
The 106 provides a PowerPC microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP documentation provides a set of specifications that define a unified personal computer architecture. PCI support allows the rapid design of systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The 106 integrates secondary cache control and a high-performance memory controller, uses an advanced, 3.3-V CMOS process technology, and is fully compatible with TTL devices. The 106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor interface of the 106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions. The 106 provides support for the following configurations of 60x processors and L2 cache: Up to four 60x processors with no L2 cache A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache controller of the Up to four 60x processors plus an externally controlled L2 cache (such as the Motorola MPC2605 integrated secondary cache)
The memory interface controls processor and PCI interactions to main memory and is capable of supporting a variety of configurations using DRAM, EDO, SDRAM, ROM, or Flash ROM. The PCI interface of the 106 complies with the PCI Local Bus Specification, Revision 2.1, and follows the guidelines in the PCI System Design Guide, Revision 1.0, for host bridge architecture. The PCI interface connects the processor and memory buses to the PCI bus, to which I/O components are connected. The PCI bus uses a 32-bit multiplexed address/data bus, plus various control and error signals. The PCI interface of the 106 functions as both a master and target device. As a master, the 106 supports read and write operations to the PCI memory space, the PCI I/O space, and the PCI configuration space. The 106 also supports PCI special-cycle and interrupt-acknowledge commands. As a target, the 106 supports read and write operations to system memory. The 106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend. The design of the MPC106 is fully static, allowing internal logic states to be preserved during all power-saving modes.
This section summarizes the major features of the 106, as follows: 60x processor interface Supports up to four 60x processors Supports various operating frequencies and bus divider ratios 32-bit address bus, 64-bit data bus Supports full memory coherency Supports optional 60x local bus slave Decoupled address and data buses for pipelining of 60x accesses Store gathering on 60x-to-PCI writes
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