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Part: MPC185
Category:
Description: Security Processor
Company: Motorola Semiconductor Products
Datasheet: Download MPC185 datasheet File size : 180 kB
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Freescale Semiconductor, Inc.
Advance Information
MPC185TS/D Rev. 2.1, 2/2003 MPC185 Security Processor Technical Summary
Freescale Semiconductor, Inc...
This technical summary provides an overview of the MPC185 Security Processor, including a brief development history, target applications, key features, typical system architecture, device architectural overview, and a performance summary.
1 Development History
The MPC185 belongs to the Smart Networks platform's S1 family of security processors developed for the commercial networking market. This product family is derived from security technologies Motorola has developed over the last 30 years, primarily for government applications. The fifth-generation execution units (EU) have been proven in Motorola semi-custom ICs and in the MPC180 and MPC190, two products in Motorola's security processor line.
2 Typical Applications
The MPC185 is suited for applications such as the following: · · · · · Edge routers Broadband access equipment eCommerce servers Wireless base stations WAP gateways
3 Features
The MPC185 is a flexible and powerful addition to any networking or computing system using the Motorola PowerQUICC II line of integrated communications processors, or any system supporting the 60x bus protocol. The MPC185 is designed to offload computationally intensive security functions, such as key generation and exchange, authentication, and bulk encryption from the host processor with PowerPC architecture. The MPC185 is optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS and 3GPP. In addition, the Motorola family of security co-processors
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
are the only devices on the market capable of executing elliptic curve cryptography which is especially important for secure wireless communications.
MPC185 features include the following:
· 2 Public Key Execution Units (PKEUs) that support the following: -- RSA and Diffie-Hellman Programmable field size up to 2048-bits -- Elliptic curve cryptography F2m and F(p) modes Programmable field size up to 511-bits 2 Data Encryption Standard Execution Units (DEUs) -- DES, 3DES -- Two key (K1, K2, K1) or Three Key (K1, K2, K3) -- ECB and CBC modes for both DES and 3DES 2 Advanced Encryption Standard Units (AESUs) -- Implements the Rinjdael symmetric key cipher -- ECB, CBC, and counter modes -- 128, 192, 256 bit key lengths 1 ARC Four Execution Unit (AFEUs) -- Implements a stream cipher compatible with the RC4 algorithm -- 40- to 128-bit programmable key 2 Message Digest Execution Units (MDEUs) -- SHA with 160-bit or 256-bit message digest -- MD5 with 128-bit message digest -- HMAC with either algorithm 1 Kasumi Execution Unit for 3GPP systems (KEUs) -- Implements F8 algorithm for encryption and F9 algorithm for authentication 1 Random number generator (RNGs) 60x compliant external bus interface, with master/slave logic -- 32-bit address/64 -bit data -- Up to 100 MHz operation 4 Crypto-channels, each supporting multi-command descriptor chains -- Static and/or dynamic assignment of crypto-execution units via an integrated controller -- Buffer size of 512 bytes for each execution unit, with flow control for large data sizes 32KB of internal scratchpad memory for key, IV and context storage 1.5V supply, 3.3V and 2.5V I/O 256 MAP BGA, 17 x 17mm package body size 1.5W power dissipation
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Freescale Semiconductor, Inc...
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4 Typical System Architecture
The MPC185 is designed to integrate easily into any system using the 60x bus protocol. It is ideal in any system using a Motorola PowerQUICC II communications processor (as shown in Figure 4-1) or a
2 MPC185 Security Processor Technical Summary For More Information On This Product, Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
PowerPC-architectured processor and memory controller. The ability of the MPC185 to be a master on the 60x bus allows the co-processor to offload the data movement bottleneck normally associated with slave devices. The host processor accesses the MPC185 through its device drivers using system memory for data storage. The MPC185 resides in the memory map of the processor, therefore when an application requires cryptographic functions, it simply creates descriptors for the MPC185 which define the cryptographic function to be performed and the location of the data. The MPC185's 60x-mastering capability permits the host processor to set up a crypto-channel with a few short register writes, leaving the MPC185 to perform reads and writes on system memory to complete the required task.
EEPROM MPC185
Freescale Semiconductor, Inc...
60x Bus MPC82xx
PCI or Local Bus
Main Memory I/O or Network Interface
Figure 4-1. MPC185 Connected to PowerQuicc II 60xBus
Figure 4-2 shows a configuration with the MPC185 communicating with the host processor via a PCI bridge, such as the MPC107.
MPC7xx, MPC74xx 60x Bus
MPC185
MPC107 PCI Bridge PCI Local Bus
Main Memory
Network Interface Card
PCI Application
Network Interface Card
Figure 4-2. MPC185 Connected to host CPU via a Bridge
MOTOROLA
MPC185 Security Processor Technical Summary For More Information On This Product, Go to: www.freescale.com
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