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Part: MPC2004
Category:
Description: 256kb And 512kb Burstram Secondary Cache Modules For Powerpc Prep/chrp Platforms
Company: Motorola Semiconductor Products
Datasheet: Download MPC2004 datasheet File size : 180 kB
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC2004/D
Advance Information
256KB and 512KB BurstRAMTM Secondary Cache Modules for PowerPCTM PReP/CHRP Platforms
The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format. Each module uses four of Motorola's 5 V 32K x 18 or 64K x 18 BurstRAMs and a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits. Bursts can be initiated with the SRAMADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the SRAMCNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more indepth description of the cache module. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. These cache modules are plug and pin compatible with the MPC2006, a 1MB synchronous module also designed for the PReP and CHRP specifications. They are also compatible with the MPC2007 and MPC2009, 256KB and 1MB respectively, asynchronous cache modules. · PowerPCstyle Burst Counter on Chip · FlowThrough Data I/O · Module Requires Both 3.3 V and 5 V Power Supplies · Multiple Clock Pins for Reduced Loading · All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible · Three State Outputs · Byte Write Capability · Fast Module Clock Rates: 66 MHz · Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM · Decoupling Capacitors for Each Fast Static RAM · High Quality MultiLayer FR4 PWB With Separate Power and Ground Planes · 182 Pin Card Edge Module · Burndy Connector, Part Number: ELF182JSC3Z50
BurstRAM is a trademark of Motorola.BurstRAM is a trademark of Motorola. PowerPC is a trademark of International Business Machines Corp.
MPC2004 MPC2005
This document contains information on a new product. Specifications and information herein are subject to change without notice.
5/95
© Motorola, Inc. 1995 MOTOROLA FAST SRAM
MPC2004·MPC2005 61
PIN ASSIGNMENT 182LEAD DIMM TOP VIEW CASE TBD
GND PD1/IDSDATA PD3 DH31 DH29 DH27 DH25 VC C 3 SRAMWE3 DH23 DH21 DH18 GND DH16 SRAMWE2 DH14 DH13 VC C 5 DH10 DH8 SRAMWE1 DH6 VC C 3 DH4 GND CLK0 GND DH1 SRAMWE0 DL31 DL30 GND DL29 DL27 DL25 VC C 5 SRAMWE7 DL23 DL21 DL19 GND DL17 SRAMWE6 DL15 DL13 GND DL10 DL8 SRAMWE5 DL6 VC C 3 DL5 DL2 GND (CLK3) NC GND (CLK4) NC GND SRAMWE4 (SRAMALE) NC VC C 3 (ADDR1A) NC (ADDR1B) NC SRAMCNTEN0 (SRAMCNTEN1) NC VC C 5 VC C 5 A27 A24 A22 A20 GND A18 A16 A15 A14 VC C 3 A10 A8 A6 GND A4 A2 A1 RESERVED VC C 5 TAG VALID TAGWE STANDBY DIRTYOUT GND
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
GND PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VC C 3 DP3 DH22 DH20 DH19 GND DH17 DP2 DH15 DH12 VC C 5 DH11 DH9 DP1 DH7 VC C 3 DH5 DH3 DH2 DH0 DP0 GND CLK1 GND DL28 DL26 DL24 DP7 VC C 5 DL22 DL20 DL18 DL16 GND DP6 DL14 DL12 DL11 GND DL9 DP5 DL7 DL4 VC C 3 DL3 DL1 DL0 GND CLK2 GND DP4 SRAMOE0 NC (SRAMOE1) VC C 3 NC (ADDR0A) NC (ADDR0B) SRAMADS0 NC (SRAMADS1) VC C 5 VC C 5 A28 A26 A25 A23 GND A21 A19 A17 A13 (See Note 1) VC C 3 NC (A12) A11 A9 GND A7 A5 A3 A0 VC C 5 TAGCLR TAG MATCH TAGOE DIRTYIN GND
NOTES: 1. This pin on the MPC2004 is a No Connect (NC). 2. S i g n a l names in (parentheses) are NC on MPC2004 and M P C 2 0 0 5 , but are actual signals on other modules in the MPC200x family. 3. All power pins (VCC5, VCC3) must be connected to appropriate supplies.
MPC2004·MPC2005 62
MOTOROLA FAST SRAM
MPC2004 (32K x 72) BurstRAM MEMORY BLOCK DIAGRAM
15 A14 A28 'FCT 244 SRAMADS0 SRAMCNTEN0 CLK0 SRAMOE0 STANDBY TSC BAA K G E MCM67M618 LW A14 A0 DQ0 DQ7 DQ8 UW DQ9 DQ16 DQ17 TSP VCC5 8 8
SRAMWE0 DH0 DH7 DP0 SRAMWE1 DH8 DH15 DP1
MCM67M618 LW A14 A0 DQ0 DQ7 TSC BAA K 15 A13 NC G E DQ8 UW DQ9 DQ16 DQ17 TSP VCC5 8 8
SRAMWE2 DH16 DH23 DP2 SRAMWE3 DH24 DH31 DP3
MCM67M618 LW A14 A0 DQ0 DQ7 TSC BAA CLK1 PD3 PD2 NC PD1 PD0 K G E DQ8 UW DQ9 DQ16 DQ17 TSP VCC5 8 8
SRAMWE4 DL0 DL7 DP4 SRAMWE5 DL8 DL15 DP5
MCM67M618 LW A14 A10 DQ0 DQ7 TSC BAA K G E 13 A14 A26 A12 A0 DQ8 UW DQ9 DQ16 DQ17 TSP 16K x 12 TAG VCCQ MATCH VALIDIN CLK VCC3 VCC5 8 8
SRAMWE6 DL16 DL23 DP6 SRAMWE7 DL24 DL31 DP7
TAG MATCH TAG VALID CLK2
A0 A11 'F04 TAGWE TAGCLR DIRTYIN TAGOE
TAG 0 TAG 11 PWRDN WESTAT, WETAG RESET DIRTYIN OESTAT, OETAG
DIRTYOUT
DIRTYOUT
MOTOROLA FAST SRAM
MPC2004·MPC2005 63
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