|
|
Part: MPC2105SG66
Category:
Description: 512kb And 1mb Burstram Secondary Cache Modules For Powerpc Prep/chrp Platforms
Company: Motorola Semiconductor Products
Datasheet: Download MPC2105SG66 datasheet File size : 40 kB
Request For quote: Find where to buy MPC2105SG66
Datasheet text preview:
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC2105C/D
512KB and 1MB BurstRAM Secondary Cache Modules for PowerPCTM PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. · · · · · · · · · · · · · PowerPCstyle Burst Counter on Chip FlowThrough Data I/O Plug and Pin Compatibility Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible Three State Outputs Byte Write Capability Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM Decoupling Capacitors for Each Fast Static RAM High Quality MultiLayer FR4 PWB With Separate Power and Ground Planes 178 Pin Card Edge Module Burndy Connector, Part Number: ELF178KSC3Z50
MPC2105C MPC2106C
178LEAD CARD EDGE TOP VIEW MPC2105C CASE 1132A01 MPC2106C CASE 113201
1
24 25
47 48
89
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
10/14/97
© Motorola, Inc. 1997 MOTOROLA FAST SRAM
MPC2105C·MPC2106C 1
MPC2105C BLOCK DIAGRAM
VSS BA13 BA28 69F618CTQ SA SBA ADSC DQA ADV SBB G DQB SE1 K 69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE2 DH16 DH23 + DP2 CWE3 DH24 DH31 + DP3 CLK0 CWE0 DH0 DH7 + DP0 CWE1 DH8 DH15 + DP1 CLK0 SRAM TIE OFF VDD '244 A13 A28
ADS0 CNTEN0 CG0
SE2 SGW
SW ZZ
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE4 DL0 DL7 + DP4 CWE5 DL8 DL15 + DP5 CLK1
ADSP
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE6 DL16 DL23 + DP6 CWE7 DL24 DL31 + DP7 CLK1
A13 A26 A1 A12 TCLR TWE CLK2 MATCH DIRTYOUT VALIDIN DIRTYIN TG
TAG: 16K x 12 + V + D A0 A13 TT1, WTD, E1 TAG0 11 SFUNC, SG RESET TAH, TAG, TAD SW E2, PWRDN TW VCCQ K MATCH TA, VALIDQ WTQ DIRTYQ VALIDD VCC DIRTYD TG
VSS VCC via 100 VDD NC VCC
A0 CLK3 CLK4 ALE ADS1 CNTEN1 CG1 ADDR0 ADDR1 PD3
= NC = NC = NC = NC = NC = NC = NC = NC = NC J3
PD2 J2 PD1 J1 PD0
Note: BA28 is tied to SA0 on SRAM; BA27 is tied to SA1 on SRAM; STANDBY is tied to SE3 on SRAM.
J0
MPC2105C·MPC2106C 2
MOTOROLA FAST SRAM
MPC2106C BLOCK DIAGRAM
BA13 BA28 BA12 69F618CTQ SA SBA ADSC DQA ADV SBB G DQB SE1 K 69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE2 DH16 DH23 + DP2 CWE3 DH24 DH31 + DP3 CLK1 69F618CTQ CWE0 DH0 DH7 + DP0 CWE1 DH8 DH15 + DP1 CLK0 SBB DQB SBA DQA K SA ADSC ADV G SE2 ADS1 CNTEN1 CG1 '244 A13 A28 A12
ADS0 CNTEN0 CG0
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE4 DL0 DL7 + DP4 CWE5 DL8 DL15 + DP5 CLK3
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE6 DL16 DL23 + DP6 CWE7 DL24 DL31 + DP7 CLK4
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
BANK A: SE2 TIED TO. VDD VIA 100 .
BANK B: SE1 TIED TO. VSS SRAM TIE OFF
A13 A26 A0 A11 TCLR TWE CLK2 MATCH DIRTYOUT VALIDIN DIRTYIN TG
TAG: 16K x 12 + V + D V CC A0 A13 TT1, WTD TAG0 11 SFUNC, SG RESET TAH, TAG, TAD SW PWRDN TW VCCQ K MATCH TA, VALIDQ WTQ DIRTYQ VALIDD E1 DIRTYD E2 TG E1 E2
VCC VSS VCC via 100 VDD NC A12 VCC VSS A12 ALE ADDR0 ADDR1 PD3 SGW ADSP
VDD
SW ZZ
= NC = NC = NC J3
PD2 J2 Note: BA28 is tied to SA0 on SRAM; BA27 is tied to SA1 on SRAM; STANDBY is tied to SE3 on SRAM. PD1 J1 PD0 J0
MOTOROLA FAST SRAM
MPC2105C·MPC2106C 3
Others parts begin by mp
|
|
|
