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Details, datasheet, quote on part number:PPC5200CBV400
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Datasheet text preview:
Advance Information
MPC5200/D Rev. 0, 07/2003 MPC5200 Hardware Specifications
Topic Page Overview ......... 1 1.1 Features ... 1 1.2 Electrical and Thermal Characteristics .......... 5 1.2.1 DC Electrical Characteristics ......5 1.2.2 Oscillator and PLL Electrical Characteristics ....10 1.2.3 AC Electrical Characteristics ....13 1.3 PLL Configuration .. 58 1.4 Package Description ....... 58 1.4.1 Package Parameters ....58 1.4.2 Mechanical Dimensions ......... 58 1.4.3 inout Listings .......60 1.5 System Design Information .... 67 1.5.1 Power UP/Down Sequencing ...... 67 1.6 Document Revision History ..... 69
NOTE:
This information was largely preliminary at the time this was published. Once first silicon has been tested, adjustments may be made to this document. For the most current information, please go to www.mobilegt.com. See the supporting information links at the bottom the that link or simply link to the MPC5200 site from the mobileGT site.
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The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPC core architecture. MPC5200 incorporates an innovative I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers and GPIOs.
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F eat ures
MPC603e series G2_LE core -- -- -- -- -- -- -- Superscalar architecture 760 Mips at 400MHz (-40 to +85 oC) 450Mips at 264MHz (-40 to +105 oC) 16k Instruction cache, 16k Data cache Double precision FPU Instruction and Data MMU Standard & Critical interrupt capability up to 132MHz operation SDRAM and DDR SDRAM support 256-MByte addressing range per CS, Two CS available 32-bit data bus
Key features are shown below.
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SDRAM / DDR Memory Interface -- -- -- --
Overview -- Built-in initialization and refresh · Flexible multi-function External Bus Interface -- -- -- -- -- · -- -- -- -- -- · · Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices 8 programmable Chip Selects Non multiplexed data access using 8/16/32 bit databus with up to 26 bit address Short or Long Burst capable Multiplexed data access using 8/16/32 bit databus with up to 25 bit address Version 2.2 PCI compatibility PCI initiator and target operation 32-bit PCI Address/Data bus 33 and 66 MHz operation PCI arbitration function
Peripheral Component Interconnect (PCI) Controller
ATA Controller -- Version 4 ATA compatible external interface--IDE Disk Drive connectivity BestComm DMA subsystem -- Intelligent virtual DMA Controller -- Dedicated DMA channels to control peripheral reception and transmission -- Local memory (SRAM 16kBytes)
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6 Programmable Serial Controllers (PSC), configurable for: -- -- -- -- UART or RS232 interface CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97 Full duplex SPI mode IrDA mode from 2400 bps to 4 Mbps
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Fast Ethernet Controller (FEC) -- Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface Universal Serial Bus Controller (USB) -- Version 1.1 Host -- Support for two independent USB slave ports
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Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.0 A/B Controller (MSCAN) -- Motorola Scalable Controller Area Network (MSCAN) architecture -- Implementation of version 2.0A/B CAN protocol -- Standard and extended data frames
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J1850 Byte Data Link Controller (BDLC) -- J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125kbps) serial data communications in automotive applications. -- Supports 4X mode, 41.6 kbps -- In-frame response (IFR) types 0, 1, 2, and 3 supported
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MPC5200 Hardware Specifications
MOTOROLA
Overview · Systems level features -- Interrupt Controller supports 4 external interrupt request lines and 47 internal interrupt sources -- GPIO / Timer functions Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/Wake Up capabilities. 8 GPIO pins with timer capability supporting input capture, output compare and pulse width modulation (PWM) functions -- -- -- -- -- · Real-time Clock with 1 second resolution Systems Protection (watch dog timer, bus monitor) Individual control of functional block clock sources Power management: Nap, Doze, Sleep, Deep Sleep modes Support of Wake Up from low power modes by different sources (GPIO, RTC, CAN)
Test / Debug features -- JTAG (IEEE 1149.1 test access port) -- Common On-Chip Processor (COP) debug port
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On-board PLL and clock generation
Figure 1 shows a simplified MPC5200 block diagram.
MOTOROLA
MPC5200 Hardware Specifications
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