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Details, datasheet, quote on part number:SN54LS192
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| Part: | SN54LS192 |
| Category: | Logic => Counters => Binary Counters |
| Description: | Presettable Bcd/decade Up/down Counter Presettable 4-bit Binary Up/down Counter |
| Company: | Motorola Semiconductor Products |
| Datasheet: | Download SN54LS192 datasheet File size : 283 kB |
| Request For quote: | Find where to buy SN54LS192
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Datasheet text preview:
PRESETTABLE BCD/DECADE UP / DOWN COUNTER PRESETTABLE 4-BIT BINARY UP / DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
SN54 / 74LS192 SN54 / 74LS193
PRESETTABLE BCD/ DECADE UP / DOWN COUNTER PRESETTABLE 4-BIT BINARY UP / DOWN COUNTER
LOW POWER SCHOTTKY
J SUFFIX CERAMIC CASE 620-09
16 1
ˇ ˇ ˇ ˇ ˇ ˇ ˇ
Low Power . . . 95 mW Typical Dissipation High Speed . . . 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects
16 1
N SUFFIX PLASTIC CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 P0 15 MR 14 TCD 13 TCU 12 PL 11 P2 10 P3 9
16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
SN54LSXXXJ SN74LSXXXN SN74LSXXXD
Ceramic Plastic SOIC
1 P1
2 Q1
3 Q0
4 CPD
5 CPU
6 Q2
7 Q3
8 GND
LOGIC SYMBOL
11 15 1 10 9
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L.
5 4 CPU CPD PL P0 P1 P2 P3 TCU TCD
CPU CPD MR PL Pn Qn TCD TCU
Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Terminal Count Down (Borrow) Output (Note b) Terminal Count Up (Carry) Output (Note b)
0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L.
12
MR Q0 Q1 Q2 Q3 14 3 2 6 7
13
NOTES: a. 1 TTL Unit Load (U.L.) = 40 ľA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.
VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 5-351
SN54 / 74LS192 ˇ SN54 / 74LS193
STATE DIAGRAMS LS192 LOGIC EQUATIONS FOR TERMINAL COUNT
TCU = Q0 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD
0
1
2
3
4
0
1
2
3
4
15
5
15
5
14
6
14
6
LS193 LOGIC EQUATIONS FOR TERMINAL COUNT
13 7
TCU = Q0 Q1 Q2 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD
13
7
12
11
10
9
8 COUNT UP
12
11
10
9
8
LS192
COUNT DOWN
LS193
LOGIC DIAGRAMS
P0 PL (LOAD) CPU (UP COUNT)
5 11 15 1
P1
10
P2
9
P3
12
TCU (CARRY OUTPUT)
S
D
Q T Q
S
D
Q T Q
S
D
Q T Q
S
D
Q
T
C
D
C
D
C
D
C
Q D
13
TCD (BORROW OUTPUT)
CPD (DOWN COUNT) MR (CLEAR)
4
14
3
2
6
7
Q0
Q1
Q2
Q3
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS
LS192
FAST AND LS TTL DATA 5-352
SN54 / 74LS192 ˇ SN54 / 74LS193
LOGIC DIAGRAMS (continued)
P0 PL (LOAD) CPU (UP COUNT)
5 12 11 15 1
P1
10
P2
9
P3
TCU (CARRY OUTPUT)
S
D
Q T Q
S
D
Q T Q
S
D
Q T Q
S
D
Q
T
C
D
C
D
C
D
C
Q D
13
TCD (BORROW OUTPUT)
CPD (DOWN COUNT) MR (CLEAR)
4
14
3
2
6
7
Q0
Q1
Q2
Q3
LS193
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS
FAST AND LS TTL DATA 5-353
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