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Details, datasheet, quote on part number:XPC8245LZU300B
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Advance Information
MPC8245EC/D Rev. 3, 7/2003 MPC8245 Integrated Processor Hardware Specifications
The MPC8245 combines a PowerPCTM MPC603e core with a PCI bridge. The PCI support on the MPC8245 will allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces. The MPC8245 also integrates a high-performance memory controller which supports various types of ROM and SDRAM. The MPC8245 is the second of a family of products that provides system-level support for industry standard interfaces with a MPC603e processor core. This document describes pertinent electrical and physical characteristics of the MPC8245. For functional characteristics of the processor, refer to the MPC8245 Integrated Processor User's Manual (MPC8245UM/D). This document contains the following topics: Topic Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Package Description" Section 1.6, "PLL Configuration" Section 1.7, "System Design Information" Section 1.8, "Document Revision History" Section 1.9, "Ordering Information" Page 1 3 5 5 32 39 44 55 58
To locate any published errata or updates for this document, refer to the web site at http://www.motorola.com/semiconductors
1.1
Overview
The MPC8245 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar MPC603e core, as shown in Figure 1.
Overview Overview
MPC8245 Additional Features: · Prog I/O with Watchpoint · JTAG/COP Interface · Power Management
Processor Core Block Processor PLL
(64-Bit) Two-Instruction Fetch
Branch Processing Instruction Unit Unit (BPU) (64-Bit) Two-Instruction Dispatch
System Register Unit (SRU)
Integer Unit (IU)
Load/Store Unit (LSU)
FloatingPoint Unit (FPU) 64-Bit
Data MMU 16-Kbyte Data Cache
Instruction MMU 16-Kbyte Instruction Cache
Peripheral Logic Bus
Peripheral Logic Block Message Unit (with I2O) DMA Controller Address (32-Bit) Central Control Unit Performance Monitor I2C I2C Controller PIC Interrupt Controller/ Timers DUART DLL Peripheral Logic PLL Configuration Registers PCI Bus Interface Unit Address Translator PCI Arbiter Data (64-Bit) Data Path ECC Controller
Data Bus (32- or 64-Bit) with 8-Bit Parity or ECC Memory/ROM/ PortX Control/Address
Memory Controller
SDRAM_SYNC_IN SDRAM Clocks PCI_SYNC_IN
5 IRQs/ 16 Serial Interrupts
Watchpoint Facility
Fanout Buffers OSC_IN
PCI Bus Clocks
32-Bit PCI Interface
Five Request/Grant Pairs
Figure 1. MPC8245 Block Diagram
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MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and I2O interface), and an I2C controller. The processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. The MPC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade-off performance for power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8245 memory space are passed to the processor bus for snooping when snoop mode is enabled. The processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. The MPC8245 can be used as either a PCI host or PCI agent controller.
1.2
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Features
Processor core -- High-performance, superscalar processor core -- Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit (LSU), system register unit (SRU), and a branch processing unit (BPU) -- 16-Kbyte instruction cache -- 16-Kbyte data cache -- Lockable L1 caches--entire cache or on a per-way basis up to three of four ways -- Dynamic power management--supports 60x nap, doze, and sleep modes Peripheral logic -- Peripheral logic bus Supports various operating frequencies and bus divider ratios 32-bit address bus, 64-bit data bus Supports full memory coherency Decoupled address and data buses for pipelining of peripheral logic bus accesses Store gathering on peripheral logic bus-to-PCI writes -- Memory interface Supports up to 2 Gbytes of SDRAM memory High-bandwidth data bus (32- or 64-bit) to SDRAM Programmable timing supporting SDRAM Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices Write buffering for PCI and processor accesses Supports normal parity, read-modify-write (RMW), or ECC Data-path buffering between memory interface and processor
Major features of the MPC8245 are as follows:
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MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
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