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Details, datasheet, quote on part number:XPC8255ACZUIFBA
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Technical Data
MPC8260AEC/D R ev. 0.9 8/2003 M P C 8 2 6xA (HiP4) Family Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for .25µm (HiP4) devices in the PowerQUICC IITM MPC8260 communications processor family. These devices include the MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266. Throughout this document, these devices are collectively referred to as the MPC826xA. The following topics are addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical and Thermal Characteristics" Section 1.2.1, "DC Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "Power Considerations" Section 1.2.4, "AC Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Bus Mode" Section 1.3.2, "PCI Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page 2 6 7 11 11 12 20 20 23 29 43 45
NOTE: Document Revision History Changes to this document are summarized in Table 22 on page 45.
Features
Figure 1 shows the block diagram for the MPC826, the HiP4 superset device. Shaded portions indicate functionality that is not available on all devices; refer to the notes.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge2,3 60x-to-Local Bridge Memory Controller Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM
IMA1,3 Microcode
60x Bus
PCI Bus2,3
32 bits, up to 66 MHz or
Local Bus
32 bits, up to 83 MHz
Communication Processor Module (CPM) Interrupt Controller 32 Kbytes Dual-Por t RAM Serial DMAs 4 Virtual IDMAs
Clock Counter System Functions
4
4
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
TC Layer Hardware1,3
Time Slot Assigner Serial Interface
8 TDM Ports5
3 MII Por ts6
2 UTOPIA Ports
Non-Multiplexed I/O
Notes: 1 MPC8264 2 MPC8265 3 MPC8266
4 5
Not on MPC8255 4 TDM ports on the MPC8255 6 2 MII ports on the MPC8255
Figure 1. MPC8266 Block Diagram
1.1
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Features
Dual-issue integer core -- A core version of the EC603e microprocessor -- System core microprocessor supporting frequencies of 150300 MHz -- Separate 16-Kbyte data and instruction caches: Four-way set associative Physically addressed LRU replacement algorithm -- PowerPC architecture-compliant memory management unit (MMU) -- Common on-chip processor (COP) test interface
The major features of the MPC826xA family are as follows:
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MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
Features
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-- High-performance (6.67.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without inlining and 1.90 Dhrystones MIPS/MHz with -- Supports bus snooping for data cache coherency -- Floating-point unit (FPU) Separate power supply for internal logic and for I/O Separate PLLs for G2 core and for the CPM -- G2 core and CPM can run at different frequencies for power/performance optimization -- Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios -- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus -- Bus supports multiple master designs -- Supports single- and four-beat burst transfers -- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller -- Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus -- Single-master bus, supports external slaves -- Eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge (MPC8265 and MPC8266 only) -- Programmable host bridge and agent -- 32-bit data bus, 66 MHz, 3.3 V -- Synchronous and asynchronous 60x and PCI clock modes -- All internal address space available to external PCI host -- DMA for memory block transfers -- PCI-to-60x address remapping
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System interface unit (SIU) -- Clock synthesizer -- Reset controller -- Real-time clock (RTC) register -- Periodic interrupt timer -- Hardware bus monitor and software watchdog timer -- IEEE 1149.1 JTAG test access port
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Twelve-bank memory controller -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals -- Byte write enables and selectable parity generation -- 32-bit address decodes with programmable bank size -- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine -- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
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