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Details, datasheet, quote on part number:MU9C1965L
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| Part: | MU9C1965L |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => LAN |
| Description: | The Lancam MP is The Widest Member of The Lancam Family. The 128-bit Memory Width is Suitable For Processing Package :LQFP |
| Company: | Music Semiconductors, Inc. |
| Datasheet: | Download MU9C1965L datasheet File size : 157 kB |
| Request For quote: | Find where to buy MU9C1965L
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Datasheet text preview:
Preliminary Data Sheet
MU9C1965A/L LANCAM® MP
APPLICATION BENEFITS
The 128 bit x 1024 LANCAM MP facilitates numerous operations: Ø Simplified switching/routing address filtering and translation
DISTINCTIVE CHARACTERISTICS
Ø Ø Ø Ø Ø Ø Ø Ø Ø
1024 x 128-bit CMOS content-addressable memory (CAM) 32-bit I/O Fast 50 ns compare speed Dual configuration register set for rapid context switching 32-bit CAM/RAM segments with MUSIC's patented partitioning /MA and /MM output flags enable faster system performance Readable Device ID Selectable faster operating mode with no wait states after a no-match Validity bit setting accessible from the Status register Single cycle reset for Segment Control register 80-pin TQFP package 5 volt (1965A) or 3.3 volt (1965L) operation
Ø Improved VLAN mapping: Ø DA, SA, Port ID to VLAN ID Ø Filter on any field Ø IP to MAC, MAC to IP filters and translation Ø DA, SA to ATM VC Ø Shiftable comparand and Mask Register 2 assists proximate matching algorithms
Ø Ø Ø
(3 2 )
M UX
D AT A (1 2 8 )
DQ 3 1 -0
(3 2 )
I/ O B U FF E R S
(3 2 )
DE M U X
D AT A (1 2 8 )
(3 2 )
S O U R C E AND D E S TI N A TI O N S E G M E NT C O U N TE R S
CO M P A RA ND M A S K REGIST ER 1 M A S K REGIST ER 2
CO M M AN DS & S T A T US /W /E /C M /EC /R E S E T CO NT RO L LO GI C
1 K X 2 VAL ID I T Y BIT S
A D D R E S S D E C O D ER
P R IO R I T Y EN C O D ER
/M A /M M 2
CO NT RO L A ND ST A T U S R E G IS T ER S
C AM A R R A Y 1 K W O RDS X 1 2 8 BI T S
10
12 FL A G LO GI C
/ FF / FI /M F /M I
Block Diagram
LANCAM, the MUSIC logo, and the phrase "MUSIC Semiconductors" are registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
1 October 1998 Rev. 1a
MU9C1965A/L LANCAM® MP
G E NERAL DESCRIPTION
The MU9C1965A and MU9C1965L LANCAM® MPs are 1024 x 128-bit content-addressable memories (CAMs), featuring a 32-bit wide interface. The wide comparand width allows the LANCAM MP to handle multiple protocols in a single search table device. Content-addressable memories, also known as associative memories, operate in the converse way to random access memories (RAM). In a RAM, the input to the device is an address and the output is the data stored at that address. In a CAM, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. As a result, a CAM searches large databases for matching data in a short, constant time period, no matter how many entries are in the database. The ability to search data words up to 128 bits wide allows large address spaces t o be searched rapidly and efficiently. A patented architecture links each CAM entry to associated data and makes this data available for use after a successful compare operation. The MUSIC LANCAM MP is ideal for address filtering and translation applications in LAN and ATM switches and routers that need the wide Comparand for Virtual LANs, VC translation, or IPV6 address recognition. The 128-bit CAM width is enough to include the DA, SA, Port ID, and Virtual LAN ID for LAN switches, or DA, SA, and VC for ATM s w i t c h e s . The LANCAM MP is also well suited for encryption, database accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM MP, the user loads the data into the Comparand register, which is automatically compared to all valid CAM locations. The device then indicates whether or not one or more of the valid CAM locations contains data that matches the target data. The status of each CAM location is determined by two validity bits at each memory location. The two bits are encoded to render four validity conditions: Valid, Skip, Empty, and Random access, as shown in Table 1. The memory can be partitioned into CAM and associated RAM segments on 32-bit boundaries, but by using one of the two available mask registers, the CAM/ RAM partitioning can be set at any arbitrary size between zero and 128 bits. The LANCAM MP's internal data path is 128 bits wide for rapid internal comparison and data movement. Vertical
Skip Bit 0 0 1 1 Empty Bit 0 1 0 1 Entry Type Valid Empty Skip RAM
cascading of additional LANCAM MPs in a daisy chain f a s h i o n extends the CAM memory depth for large databases. Cascading requires no external logic. Loading data to the Control, Comparand, and mask registers automatically triggers a compare. Compares may also be initiated by a command to the device. Associated RAM data is available immediately after a successful compare o p e r a t i o n . The Status register reports the results of compares including all flags and addresses. Two mask registers are available and can be used in two different ways: to mask comparisons or to mask data writes. The random access validity type allows additional masks to be stored in the CAM array where they may be retrieved rapidly. A simple four-wire control interface and commands loaded into the Instruction decoder control the device. A powerful instruction set increases the control flexibility and minimizes software overhead. Additionally, dedicated pins for match and multiple match flags enhance performance when the device is controlled by a state machine. These and other features make the LANCAM MP a powerful associative memory that drastically reduces search delays.
Table 1: Entry Types vs. Validity Bits
Rev. 1a
2
MU9C1965A/L LANCAM® MP
P I N DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL) The /E input enables the device while LOW. The falling edge registers the control signals /W, /CM, /EC. The rising edge locks the daisy chain, turns off the DQ pins, and clocks the Destination and Source Segment counters. The four cycle types enabled by /E are shown in Table 2.
DQ310 (Data Bus, I/O, TTL) The DQ310 lines convey data, commands, and status to and from the LANCAM MP, as shown in Table 3. /W and /CM control the direction and nature of the information that flows to or from the device. When /E is HIGH, DQ310 go to Hi-Z. /MF (Match Flag, Output, TTL) The /MF output goes LOW when one or more valid matches occur during a Compare cycle. /MF becomes valid after /E goes HIGH on the cycle that enables the daisy chain (on the first cycle that /EC is registered LOW by the previous falling edge of /E; see Figure 5 on page 15). In a daisy chain, valid match(es) in higher priority devices are passed from the /MI input to /MF. If the daisy chain is enabled but the match flag is disabled in the Control register, the /MF output only depends on the /MI input of the device (/MF= /MI). /MF is HIGH if there is no match or when the daisy chain is disabled (/E goes HIGH when /EC was HIGH on the previous falling edge of /E). The System Match flag is the /MF pin of the last device in the daisy chain. /MF will be reset when the active configuration register set is changed.
/W LOW LOW HIGH HIGH
/CM Cycle Type LOW Command Write Cycle HIGH Data Write Cycle LOW Command Read Cycle HIGH Data Read Cycle Table 2: I/O Cycles
/W (Write Enable, Input, TTL) The /W input selects the direction of data flow during a device cycle. /W LOW selects a Write cycle and /W HIGH selects a Read cycle. /CM (Data/Command Select, Input, TTL) T h e /CM input selects whether the input signals on DQ310 are data or commands. /CM LOW selects Command cycles and /CM HIGH selects Data cycles. /EC (Enable Daisy Chain, Input, TTL) The /EC signal performs two functions. The /EC input enables the /MF output to show the results of a comparison, as shown in Figure 5 on page 15. If /EC is LOW at the falling edge of /E in a given cycle, the /MF output is enabled. Otherwise, the /MF output is held HIGH. The /EC signal also enables the /MF/MI daisy chain, which serves to select the device with the Highest-Priority Match in a string of LANCAMs. Tables 6a and 6b on page 12 explain the effect of the /EC signal on a device with or without a match in both Standard and Enhanced modes. /EC must be HIGH during initialization.
G ND
DQ8
DQ7
DQ6
DQ5
DQ4 DQ3
DQ2
DQ1 DQ0
G ND G ND
G ND 42
60
59
58
57
56
55 54
53 52
51
50 49
48
47
46
45
44
43
41
G ND
V CC
V CC
/C M
/ MA
/EC
/ FI
G ND G ND DQ9 D Q 10 D Q 11 NC V CC V CC TE S T 2 NC G ND G ND D Q 12 D Q 13 G ND G ND D Q 14 D Q 15 D Q 16 NC
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32
NC / FF / MI / MF / MM G ND G ND /R ESET V CC V CC /E /W V CC V CC TE S T 1 NC D Q 31 D Q 30 G ND G ND
80-Pin TQFP (Top View)
31 30 29 28 27 26 25 24 23 22 21
10
11
12 13
14
15
16
17
18 D Q 28
19 D Q 29
D Q 17
D Q 18
D Q 19
D Q 20
V CC D Q 21
D Q 22
D Q 23
D Q 24
D Q 25
D Q 26 D Q 27
G ND
G ND
G ND
G ND
G ND
Pinout Diagram
3
G ND
20
1
2
3
4
5 6
7
8
9
Rev. 1a
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