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Details, datasheet, quote on part number:MU9C2480B
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| Part: | MU9C2480B |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => LAN |
| Description: | Lancam B is The Smallest, MOSt Cost Effective Lancam Offering Yet. 64 Bits Wide, With a High Speed 16-bit Interface Package :LQFP |
| Company: | Music Semiconductors, Inc. |
| Datasheet: | Download MU9C2480B datasheet File size : 482 kB |
| Request For quote: | Find where to buy MU9C2480B
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Datasheet text preview:
Data Sheet Draft
LANCAM B Family
APPLICATION BENEFITS
· · New low-cost LANCAM family in a space-saving TQFP package Fast speed allows processing of both DA and SA within 450 ns, equivalent to 138 ports of 10 Base-T or 13 ports of 100 Base-T Ethernet Full CAM features allow all operations to be masked on a bit-by-bit basis Powerful, LANCAM A/L compatible instruction set for any list processing need Shiftable Comparand and Mask registers assist in proximate matching algorithms Cascadable to any practical length with no performance penalties Industrial temperature grades for harsh environments Dual footprint connections to conserve board space 3.3 Volt for lower power systems
DISTINCTIVE CHARACTERISTICS
· · · · · · · · · · · · · · High density CMOS Content Addressable Memory (CAM) 1K (1480B), 4K (4480B), 8K (8480B) words 64-bit per word memory organization 16-bit I/O Fast 50 ns compare speed Dual configuration register set for rapid context switching 16-bit CAM/RAM segments with MUSIC's patented partitioning /MA and /MM output flags to enable faster system performance Readable Device ID Selectable faster operating mode with no wait states after a no-match Validity bit setting accessible from the Status register Single cycle reset for Segment Control register 44- and 64-pin TQFP package 3.3 Volt operation
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DATA (16)
MUX
DATA (64) VCC GND
DQ (15--0)
(16)
I/O BUFFERS
DATA (16)
TRANSLATE 802 .3/80 2.5
DATA (16)
DEMU X
DATA (64)
COMMANDS & STATUS (16) SOURCE AND DESTINATION SEGMENT COUNTERS COMPARAND* MASK 1 MASK 2
ADDRESS DECODER
INSTRUCTION (W/O)* /W CONTROL /CM /RESET 16 PAGE ADDRESS (LOCAL ) DEVICE SELECT (GLOBAL) /EC STATUS (15-0) ( R/O)* /MM, /FL STATUS (31-16) (R/O) REGISTER SET 2 MATCH ADDR & /MA F LAG N+1 ADDRESS NEXT FREE ADDRESS (R/O) CONTROL SEGMENT CONTROL N
2N X 2 VALIDITY BITS
PRIORITY ENCODER
/E
/MA /MM
CAM ARRA Y 2N WORDS X 64 BITS
2
/FF MATCH AND FLAG LOGIC /FI /MF /MI
Figure 1: LANCAM B Family Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors.
October 20, 2000 Rev. 1
LANCAM B Family
General Description
GENERAL DESCRIPTION
The LANCAM consists of various depths of 64-bit Content Addressable Memories (CAMs), with a 16-bit wide interface. CAMs, also known as associative memories, operate in the converse way to random access memories (RAM). In RAM, the input to the device is an address and the output is the data stored at that address. In CAM, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. As a result, CAM searches large databases for matching data in a short, constant time period, no matter how many entries are in the database. The ability to search data words up to 64 bits wide allows large address spaces to be searched rapidly and efficiently. A patented architecture links each CAM entry to associated data and makes this data available for use after a successful compare operation. The MUSIC LANCAMs are ideal for address filtering and translation applications in LAN switches and routers. The LANCAMs are also well suited to encryption, database accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM, the user loads the data into the Comparand register, which is automatically compared to all valid CAM locations. The device then indicates whether or not one or more of the valid CAM locations contains data that matches the target data. The status of each CAM location is determined by two validity bits at each memory location. The two bits are encoded to render four validity conditions: Valid, Empty, Skip, and RAM, shown in Status Register Bits on page 24 (bits 29:28). The memory can be partitioned into CAM and associated RAM segments on 16-bit boundaries, but by using one of the two available Mask registers, the CAM/RAM partitioning can be set at any arbitrary size between zero and 64 bits. The LANCAM's internal data path is 64 bits wide for rapid internal comparison and data movement. Vertical cascading of additional LANCAMs in a daisy chain fashion extends the CAM memory depth for large databases. Cascading requires no external logic. Loading data to the Control, Comparand, and Mask registers automatically triggers a compare. Compares also may be initiated by a command to the device. Associated RAM data is available immediately after a successful compare operation. The Status register reports the results of compares including all flags and addresses. Two Mask registers are available and can be used in two different ways: to mask comparisons or to mask data writes. The RAM validity type allows additional masks to be stored in the CAM array where they may be retrieved rapidly. A simple four-wire control interface and commands loaded into the Instruction decoder control the device. A powerful instruction set increases the control flexibility and minimizes software overhead. Additionally, dedicated pins for match and multiple-match flags enhance performance when the device is controlled by a state machine. These and other features make the LANCAM a powerful associative memory that drastically reduces search delays.
2
Rev. 1
Pin Descriptions
LANCAM B Family
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 25 for more information.
/MM /FF /FI /CM /EC GND DQ0 DQ1 DQ2 DQ3 VCC
NC NC GND DQ4 DQ5 VCC VCC TEST2 GND GND GND GND DQ6 DQ7 VCC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC /MM /FF /FI /CM /EC GND GND DQ0 DQ1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC /MA /MI /MF GND GND /RESET VCC VCC TEST1 /E /W GND GND NC NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DQ2 DQ3 VCC NC NC
34 35 36 37 38 39 40 41 42 43 44
GND DQ4 DQ5 VCC VCC TEST2 GND GND DQ6 DQ7 VCC
1 2 3 4 5 6 7 8 9 10 11
44-Pin TQFP (Top View)
33 32 31 30 29 28 27 26 25 24 23
/MA /MI /MF GND /RESET VCC VCC TEST1 /E /W GND
64-Pin TQFP (Top View)
Figure 2: 44-Pin TQFP /E (Chip Enable, Input, TTL) The /E input enables the device while LOW. The falling edge registers the control signals /W, /CM, and /EC. The rising edge locks the daisy chain, turns off the DQ pins, and clocks the Destination and Source Segment counters. The four cycle types enabled by /E are shown in Table 1. Table 1: I/O Cycles
/W LOW LOW HIGH HIGH /CM LOW HIGH LOW HIGH Cycle Type Command Write Cycle Data Write Cycle Command Read Cycle Data Read Cycle
/W (Write Enable, Input, TTL) The /W input selects the direction of data flow during a device cycle. /W LOW selects a Write cycle and /W HIGH selects a Read cycle. /CM (Data/Command Select, Input, TTL) The /CM input selects whether the input signals on DQ150 are data or commands. /CM LOW selects Command cycles and /CM HIGH selects Data cycles. /EC (Enable Daisy Chain, Input, TTL) The /EC signal performs two functions. The /EC input enables the /MF output to show the results of a comparison, as shown in Figure 9 on page 14. If /EC is LOW at the falling edge of /E in a given cycle, the /MF output is enabled. Otherwise, the /MF output is held HIGH.
Rev. 1
22 21 20 19 18 17 16 15 14 13 12 GND DQ15 DQ14 DQ13 DQ12 GND DQ11 DQ10 DQ9 DQ8 GND
The /EC signal also enables the /MF/MI daisy chain, which serves to select the device with the highest-priority match in a string of LANCAMs. Table 4 explains the effect of the /EC signal on a device with or without a match in both Standard and Enhanced modes. /EC must be HIGH during initialization. DQ150 (Data Bus, I/O, TTL) The DQ150 lines convey data, commands, and status to and from the LANCAM. /W and /CM control the direction and nature of the information that flows to or from the device. When /E is HIGH, DQ150 go to HIGH-Z. /MF (Match Flag, Output, TTL) The /MF output goes LOW when one or more valid matches occur during a compare cycle. /MF becomes valid after /E goes HIGH on the cycle that enables the daisy chain (on the first cycle that /EC is registered LOW by the previous falling edge of /E; see Figure 9 on page 14). In a daisy chain, valid match(es) in higher priority devices are passed from the /MI input to /MF. If the daisy chain is enabled but the match flag is disabled in the Control register, the /MF output only depends on the /MI input of the device (/MF=/MI). /MF is HIGH if there is no match or when the daisy chain is disabled (/E goes HIGH when /EC was HIGH on the previous falling edge of /E). The System Match flag is the /MF pin of the last device in the daisy chain. /MF is reset when the active configuration register set is changed. 3
DQ9 DQ8 GND GND NC
Figure 3: 64-Pin TQFP
NC GND GND DQ15 DQ14 DQ13 DQ12 GND GND DQ11 DQ10
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