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Details, datasheet, quote on part number:MU9C8K64-70TDC
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| Part: | MU9C8K64-70TDC |
| Category: | Communication => Network => Network Processors => Co-Processors |
| Description: | The MU9C Routing Co-processor Performs 64-bit Binary Searches For Layer 2 Ethernet And Layer 4 Flow Recognition Lookups. Package :LQFP |
| Company: | Music Semiconductors, Inc. |
| Datasheet: | Download MU9C8K64-70TDC datasheet File size : 627 kB |
| Request For quote: | Find where to buy MU9C8K64-70TDC
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Datasheet text preview:
Data Sheet
MU9C Routing Coprocessor (RCP) Family
APPLICATION BENEFITS
· 28 million IPv4 packets per second supports up to 18 Gb Ethernet or 7 OC-48 ATM ports at wire speed · Exact match on MAC addresses · Processes DA and SA within 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed · Mixed mode L3 and L2 single search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed · Directly addresses external RAM containing associated data of any width · Hardware control states directly address memory and registers; Instruction and Status registers for optional software control
DISTINCTIVE CHARACTERISTICS
· 4K and 8K x 64-bit words · 64-bit binary compares · 35 ns deterministic compare and output time · 32-bit Data I/O port · 16-bit Match Address Output port · Address/Control bus directly controls device operations for faster operation or higher throughput · Seven selectable mask registers · Synchronous operation · Cascadable for increased depth · Extensive set of control states for flexibility · JTAG interface · 100-pin LQFP package; 3.3 Volt operation
DQ310 /VB
/E
/CS1
/CS2
/W
/OE
/AV AC Bus
/DSC
COMPARAND REGISTER MASK REGISTERS 17 ADDRESS REGISTER CONFIGURATION REGISTER STATUS REGISTER
AA Bus PA30
CONTROL AND ADDRESS DECODER
INSTRUCTION REGISTER DEVICE SELECT REGISTER
/RESET
TCLK
TMS
TDI
TDO
/TRST
PRIORITY ENCODER AND FLAG LOGIC
/FI /F F
4 K x 64 Word (MU9C4K64) 8 K x 64 Word (MU9C8K64) Address Database
/M I /M F
/M M
Figure 1: Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors.
June 1 2002 Rev. 6
MU9C Binary Routing Coprocessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MU9C RCP family consists of 4K and 8K x 64-bit Routing Coprocessors (RCPs) with a 32-bit wide data interface. The device is designed for use in layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MU9C RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce some jitter on the latency of the global system. Address fields from the packet header are compared against a list of entries stored in the array. As a result of the comparison, the MU9C RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored. A set of control states provides a powerful and flexible control interface to the MU9C RCP. This control structure allows memory read and write, register read and write, data move, comparison, validity control, addressing control, and initialization operations. The MU9C RCP architecture uses direct hardware control of the device and an independent bus for returning match results. Software control is also supported for systems where maximum performance is not needed.
OPERATIONAL OVERVIEW
The MU9C RCP is designed to act as an address translator for lookup tables in layer 2 switches. Refer to Figure 2 for a simplified block diagram of a switch. During normal operation, the controller extracts the address information from an arriving packet to form the comparand, which is then compared against the contents of the MU9C RCP. The MU9C RCP generates an index that is used to access the data in an external RAM, which holds the destination port for accessing the network. The controller reads the data from the RAM and forwards the packet. The validity of a location in the Address Database is determined by an extra bit called the Validity bit. This bit is set and reset either with an index or an associative match. Therefore, when a new entry is written to the database, its Validity bit is set valid. The index at which a write takes place is driven onto the PA:AA bus, so that output port data can be written simultaneously into the external RAM at the correct index. When a database location is deleted, the Validity bit for that entry is reset, and the index of the location is driven onto the Active Address bus. This simple mechanism allows easy maintenance of the tables in both the database and the external RAM. The MU9C RCP supports simple daisy chained vertical cascading that serves to prioritize multiple devices and provides system-level match and full indication. If the slight timing overhead associated with the daisy chain is unacceptable, the MU9C RCP is designed to facilitate external prioritization across multiple devices.
Packet Stream
Controller
Switch Control and Packet Data
RCP Control
Network Address
Data
Switch Fabric
MU9C
RAM Address
RAM
Figure 2: Switch Block Diagram
2
Rev. 6
Pin Descriptions
MU9C Binary Routing Coprocessor (RCP) Family
PIN DESCRIPTIONS
Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
software control is selected, the state of the AC bus does not affect the operation of the device.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word is performed, the DSC input determines whether bits 310 (DSC LOW) or bits 6332 (DSC HIGH) are accessed. Access to 32 bit registers require that DSC be held LOW.
DQ310 (Data Bus, Three-state, Common Input/ Output)
The DQ310 lines convey data to and from the MU9C RCP. When the /E input is HIGH the DQ310 lines are held in their high-impedance state. The /W input determines whether data flows to or from the device on the DQ310 lines. The source or destination of the data is determined by the AC bus, DSC, and the /AV line. During a Write cycle, data on the DQ310 lines is registered by the falling edge of /E.
AA120/AA110 (Active Address, Output)
The AA bus conveys the Match address, the Next Free address, or Random Access address, depending on the most recent memory cycle. The /OE input enables the AA bus; when the /OE input is HIGH, the AA bus is in its high-impedance state; when /OE is LOW the AA bus is active. In a vertically cascaded system after a Comparison cycle, Write at Next Free Address cycle or Read/Write at Highest-Priority match, only the highest-priority device will enable its AA bus, regardless of the state of the /OE input. In the event of a mismatch in the Address Database after a Compare cycle, or after a Write at Next Free Address cycle into an already full system, the lowest-priority device will drive the AA bus with all 1s. The AA bus is latched when /E is LOW, and are free to change only when /E is HIGH.
AC120/AC110 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys address or control information to the MU9C RCP, depending on the state of the /AV input. When /AV is LOW then the AC bus carries an address; when /AV is HIGH the AC bus carries control information. Data on the AC bus is registered by the falling edge of /E. When
VSS PA3 PA2 PA1 PA0 VSS A A 1 2/ N C * A A 11 A A 10 AA9 AA8 VSS AA7 AA6 AA5 AA4 V DD AA3 AA2 AA1 AA0
DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS / MF /FF V DD / MI /FI VSS /MM DS C
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
AA12/NC* AC11 AC10 AC9 AC8 VSS AC7 AC6 AC5 AC4 VDD AC3 AC2 AC1 AC0 VSS TDO TDI TMS TCLK
MU9CxK64 100-Pin LQFP (Top View)
D Q 16 D Q 17 D Q 18 D Q 19 V DD D Q 20 D Q 21 D Q 22 D Q 23 VSS D Q 24 D Q 25 D Q 26 D Q 27 V DD D Q 28 D Q 29 D Q 30 D Q 31 VSS /E /W / C S1 / C S2 / OE VSS / AV / VB /RESET /TRST
* NC on MU9C4K64
Figure 3: MU9C RCP Pinout
Rev. 6
3
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