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Details, datasheet, quote on part number:MUAA2K80
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| Part: | MUAA2K80 |
| Category: | Communication => Network => Network Processors => Co-Processors |
| Description: | The Muaa Routing Co-processor Excels at Layer 2 And Layer 4 Header Processing For High-performance Ethernet Switches And Routers Package :PQFP |
| Company: | Music Semiconductors, Inc. |
| Datasheet: | Download MUAA2K80 datasheet File size : 341 kB |
| Request For quote: | Find where to buy MUAA2K80
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Datasheet text preview:
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MUAA Routing Co-Processor (RCP) Family
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· High-performance MAC Address processor for multiport switches and routers (up to 48 10/100Mb or 4 Gigabit Ethernet at wire speed) Layer 4 flow recognition for Quality of Service up to 16.7 million packets per second ARP cache manager/IP address caching at 12.5 million packets per second Synchronous interfaces and programmable priority between ports for simplicity of design Learn, age, and auto-age functions with "virtual queues" keeping track of aged and learned entries Transparent cascade of up to four devices without external logic, software setup, or performance hit
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· · · · · 2K and 8K x 80-bit partitionable CAM/RAM data field in address database 32-bit synchronous port with separate inputs and outputs; optional 16-bit configuration 32-bit bi-directional processor port; optional 16-bit configuration Pipelined operation Operations performed from the synchronous port or processor port; all flags independently available to both ports 9-bit internal time stamp 50 MHz clock 160-pin PQFP package 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers IEEE 1149.1 (JTAG) compliant
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The MUSIC MUAA Routing Co-Processor (RCP) family consists of 80-bit wide content-addressable memories (CAMs), available in depths of 2K and 8K words. The CAM/RAM associated data partition is programmable from 32 bits of CAM and 48 bits of associated data, to 80 bits of CAM and 0 bits of RAM. The MUAA RCP can perform normal routing functions such as search, insert, and delete on single entries and can age multiple entries simultaneously. In addition, there is a learn instruction, particularly useful in networking applications. For maximum flexibility all the operations may be performed either through the processor port or through the synchronous port. Operations may occur on both ports simultaneously; the port with the highest priority will gain access first if both ports require a read or write into the CAM array simultaneously. The synchronous interface consists of 32-bit wide input and output ports, both of which may be configured as 16 bits. The data is multiplexed into and out of the CAM and RAM associated data field. Where input or output data is wider than the port, it is loaded or unloaded in multiple cycles starting with the least significant word. Internally the device is pipelined; once an operation is started on the synchronous port the next operation may be loaded and the results of the previous operation unloaded, thus maximizing device throughput. Multiple MUAA RCPs may be chained transparently to provide deeper memory. No software configuration is necessary. Each MUAA RCP detects where it is in the chain from the chaining pins on the previous device. A register is provided to inform the host of the total available CAM memory and the number of CAMs chained. All operations to the chained CAM are totally transparent. No individual device selection or addressing is required. The MUSIC MUAA RCP has aging, auto-aging, and learning functions. All entries have a 9-bit time stamp and may be marked as static to prevent the aging function from deleting them. When auto aging is enabled it may be configured to have higher or lower priority access than the ports. Two internal virtual queues of learned and aged entries are available. As entries are learned or aged out they are tagged as such and may be read from the device through either of the ports. This feature enables simple host management of aged out and learned entries. IEEE Standard. 1149.1 (JTAG) testability is implemented providing BYPASS, SAMPLE/PRELOAD, EXTEST, CLAMP, and HIGH-Z functions.
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Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3 Volt CMOS level. All input and bi-directional pins are 5-Volt tolerant, except for CLK. Never leave inputs floating except where indicated. The CAM architecture draws large currents during search operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
VCC DOUT0 GND DIN31 DIN30 DIN29 DIN28 DIN27 GND DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 VCC DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 GND DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 VCC DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND DOUT1 DOUT2 DOUT3 DOUT4 VCC DOUT5 DOUT6 DOUT7 GND DOUT8 DOUT9 DOUT10 DOUT11 VCC DOUT12 DOUT13 DOUT14 DOUT15 GND DOUT16 DOUT17 DOUT18 DOUT19 VCC DOUT20 DOUT21 DOUT22 DOUT23 GND DOUT24 DOUT25 DOUT26 DOUT27 VCC DOUT28 DOUT29 DOUT30 DOUT31 GND
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
160-Pin PQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VCC CHAINDN CHAINUP GND CHAIN3 CHAIN2 CHAIN1 CHAIN0 GND CHAINCS PROCD31 PROCD30 PROCD29 PROCD28 PROCD27 PROCD26 PROCD25 PROCD24 VCC PROCD23 PROCD22 PROCD21 PROCD20 PROCD19 PROCD18 GND PROCD17 PROCD16 PROCD15 PROCD14 PROCD13 PROCD12 VCC PROCD11 PROCD10 PROCD9 PROCD8 PROCD7 PROCD6 GND
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D,1>@ ,QSXW IN[31:0] are synchronous port data input pins. Data is loaded into the MUAA RCP right aligned, least significant word first. D ',1( ,QSXW IN is sampled by the rising edge of CLK when /DINE is asserted.
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VCC CLK GND /MF /FF /DOUTVAL ID DINREAD Y INT PROCREADY TDO GN D TDI TMS TCK /TRST /OE /DOUTE /D INE OP0 OP1 OP2 OP3 VCC PROCA0 PROCA1 PROCA2 PROCA3 PROCA4 PROCA5 R/W /PCS /RESET GND PROCD0 PROCD1 PROCD2 PROCD3 PROCD4 PROCD5 VCC
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O 23>@ ,QSXW P[3:0] is a synchronous port operation to be performed on the data applied to the DIN pins. OP is sampled by the rising edge of CLK when /DINE is asserted. When loading the CAM/RAM words to DIN, OP is set to LOAD except for the last word. OP for the last word is set to the desired operation.
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