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Details, datasheet, quote on part number:MUAC4K64
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Datasheet text preview:
Data Sheet
MUAC Routing CoProcessor (RCP) Family
APPLICATION BENEFITS
· · · · Longest Prefix Match searches of IPv4 addresses 28 million IPv4 packets per second supports up to 18 Gb Ethernet or 7 OC-48 ATM ports at wire speed Exact match on MAC addresses Processes DA and SA within 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed Mixed mode L3 and L2 single search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed Directly addresses external associated data of any width RAM containing
DISTINCTIVE CHARACTERISTICS
· · · · · · · · · · · · 4K and 8K x 64-bit words 32-bit ternary or 64-bit binary compares 35 ns deterministic compare and output time 32-bit Data I/O port 16-bit Match Address Output port Address/Control bus directly controls device operations for faster operation or higher throughput Seven selectable mask registers Synchronous operation Cascadable for increased depth Extensive set of control states for flexibility JTAG interface 100-pin TQFP package; 3.3 Volt operation
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Hardware control states directly address memory and registers; Instruction and Status registers for optional software control
DQ310 /VB
/E /CS1 /CS2 /W /OE /AV AC Bus /DSC /RESET TCLK TMS TDI TDO /TRST CONTROL AND ADDRESS DECODER COMPARAND REGISTER MASK REGISTERS 17 ADDRESS REGISTER PA30 CONFIGURATION REGISTER STATUS REGISTER INSTRUCTION REGISTER DEVICE SELECT REGISTER PRIORITY ENCODER AND FLAG LOGIC AA Bus
4 K x 64 Word (MUAC4K64) 8 K x 64 Word (MUAC8K64) Address Database
/FI /F F /M I /M F /MM
Figure 1: Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors.
March 6, 2001 Rev. 4a
MUAC Routing CoProcessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MUAC RCP family consists of 4K and 8K x 64-bit Routing CoProcessors (RCPs) with a 32-bit wide data interface and a 32-bit ternary compare instruction. The device is designed for use in layer 3 switches, routers, and layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MUAC RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce some jitter on the latency of the global system. Address fields from the packet header are compared against a list of entries stored in the array. As a result of the comparison, the MUAC RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored. A set of control states provides a powerful and flexible control interface to the MUAC RCP. This control structure allows memory read and write, register read and write, data move, comparison, validity control, addressing control, and initialization operations. The MUAC RCP architecture uses direct hardware control of the device and an independent bus for returning match results. Software control is also supported for systems where maximum performance is not needed.
OPERATIONAL OVERVIEW
The MUAC RCP is designed to act as an address translator for lookup tables in layer 3 switches, routers, and layer 2 switches. Refer to Figure 2 for a simplified block diagram of a switch. During normal operation, the controller extracts the address information from an arriving packet to form the comparand, which is then compared against the contents of the MUAC RCP. The MUAC RCP generates an index that is used to access the data in an external RAM, which holds the destination port for accessing the network. The controller reads the data from the RAM and forwards the packet. A unique feature of the MUAC RCP is its ternary comparison that processes IPv4 CIDR addresses in a single cycle. The bits of each MUAC RCP word are paired, such that each pair can contain two binary values (0,1) or one ternary (0,1,X= "Don't Care") value. A ternary value uses two bits, pairing bit n from the first 32 bits (31-0) with bit n+32. When storing a ternary 0 or 1, the value to be stored is written into bit n (0<=n<=31), and the complement of the value is written to bit n+32. Thus, a ternary 0 written to ternary pair 7 would consist of a 0 stored in bit 7 and a 1 stored in bit 39. When storing a ternary X, 0 is written to both bits in the pair. Using bit pairs that are 32 bits apart simplifies the computation of the pair by a processor. Assume that the ternary value we wish to store is contained in two 32-bit processor words. Word A contains the value to be stored and word M contains a mask value, with a 0 in each position at which an X is to be stored. The value to be written to bits 31-0 of the MUAC RCP is (A&M) and the value to be written to bits 63-32 of the MUAC RCP is (~A&M). A special instruction, CMPT DQ, performs the ternary comparison processing for IPv4 CIDR addresses. The data on the DQ bus are used directly as both the comparand and compare mask bits 310, and the one's complement of the 2 DQ bus data are used as both the comparand and compare mask bits 6332. As a result, this instruction matches a DQ bit of 0 with bit pairs storing both 0 and X, and a DQ bit of 1 matches bit pairs storing both 1 and X. IPv4 CIDR addresses are prioritized by placing their ternary-encoded values into the MUAC RCP memory such that entries with longer netmasks (longer matches) have higher priority (lower indices). Thus, when the MUAC RCP performs a ternary comparison, it will return the index of the longest matching entry. Typically, the system is initialized by a processor that writes routing table information into the MUAC RCP. The index at which a write takes place is driven onto the PA:AA bus, so that output port data can be written simultaneously into the external RAM at the correct index. The validity of a location in the Address Database is determined by an extra bit called the Validity bit. This bit is set and reset either with an index or an associative match. Therefore, when a new entry is written to the database, its Validity bit is set valid. When a database location is deleted, the Validity bit for that entry is reset, and the index of the location is driven onto the Active Address bus. This simple mechanism allows easy maintenance of the tables in both the database and the external RAM. The MUAC RCP supports simple daisy chained vertical cascading that serves to prioritize multiple devices and provides system-level match and full indication. If the slight timing overhead associated with the daisy chain is unacceptable, the MUAC RCP is designed to facilitate external prioritization across multiple devices. For layer 2 applications, the MAC addresses are processed in a binary mode, and the MUAC RCP looks for an exact match. An MUAC RCP can be used to process both MAC addresses and IPv4 CIDR in the same device.
Rev. 4a
Operational Overview
MUAC Routing CoProcessor (RCP) Family
Packet Stream
Controller
Switch Control and Packet Data
RCP Control
Network Address
Data
Switch Fabric
RAM Address MUAC RAM
Figure 2: Switch Block Diagram
Rev. 4a
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