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Details, datasheet, quote on part number:N16T1618C2A
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Datasheet text preview:
NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com
N16T1618C2(D1/A1)A
Advance Information
16Mb Ultra-Low Power Asynchronous CMOS PSRAM
1M x 16 bit Overview
The N16T1618C2(D1/A1)A is an integrated memory device containing a 16 Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 1,048,576 words by 16 bits. It is designed to be compatible in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device is available in a 2 CE (chip enable) version and two ZZ (deep sleep) versions. The ZZ version includes several power saving modes: a deep sleep mode where data is not retained in the array and partial array refresh mode where data is retained in a portion of the array. Both these modes reduce standby current drain. The VFBGA package has separate power rails, VccQ and VssQ for the I/O to be run from a separate power supply from the device core.
Features
· Dual voltage for Optimum Performance VCCQ and VSSQ for separate I/O power rails Vcc - 1.65V to 2.2 V Vccq - 1.65V to 3.6V · Fast Cycle Times TACC < 85 nS · Very low standby current ISB < 40µA @ 1.8V · Very low operating current Icc < 25mA · Memory expansion with CE and OE · Automatic power down mode · 48-Pin VFBGA, Wafers Available
Product Family
Part Number
N16T1618C2AZ N16T1618D1AZ N16T1618A1AZ
Feature
2 CE Deep Sleep Disabled Deep Sleep Active
Package Operating Type Temperature
Power Supply
Speed
Standby Current (ISB), Max
40 µA @ 1.8V
Operating Current (Icc), Max
48 - BGA
-30oC to +85oC
1.65V - 2.2V
85ns @ 1.65V
3 mA @ 1MHz
Pin Configuration
1 A B C D E F G H
LB I/O8 I/O9
Pin Descriptions
3
A0 A3 A5 A1 7
2
OE UB I/O10
4
A1 A4 A6 A7 A1 6 A1 5 A1 3 A1 0
5
A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6
CE2/ ZZ I/O0 I/O2 V CC VS S I/O6 I/O7 NC
Pin Name A0-A19 WE CE1 CE2 ZZ OE LB UB I/O0-I/O15 VC C VSS VC C Q VSSQ DNU
Pin Function Address Inputs Write Enable Input Chip Enable Input Chip Enable Input (only for CE2 device) Deep Sleep Input (only for A1 or D1 deep sleep device) Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Groun d Power I/O pin only Ground I/O pin only Do Not Use (or connect to VSS)
VSSQ I/O11
VCCQ I/O12 DNU I/O14 I/O13 I/O15 A1 8 A1 9 A8 A1 4 A1 2 A9
48 Pin BGA (top) 6 x 8 mm
Stock No. 23183 - 04 4/03 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc. Functional Block Diagram
N16T1618C2(D1/A1)A
Advance Information
Address Inputs A0 - A19
Address Decode Logic
1024K x 16 Memory Array
Input/ Output Mux and Buffers
I/O0 - I/O7
CE1 CE2 1 WE OE UB LB
I/O8 - I/O15 Control Logic
ZZ 2
Functional Description
CE1 H X X L L L CE2 1 X L X H H H WE X X X L H H OE X X X X5 L H UB/LB X X H L3 L3 L3 ZZ 2 H H H H H H I/O3 High Z High Z High Z Data In Data Out High Z MODE Standby4 Standby4 Standby4 Write5 Read Active POWER Standby Standby Standby Active -> Standby6 Active -> Standby6 Standby6
1.) Only on the two-CE option device. 2. Only on the one-CE option device with sleep mode. 3. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - IO7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. If both UB and LB are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE1 or CE2. 4. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 5. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. 6. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any external influence.
Capacitance1
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23183 - 04 4/03 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc. Absolute Maximum Ratings1
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER
N16T1618C2(D1/A1)A
Advance Information
Rating 0.3 to VCC+0.3 0.3 to 4.0 500 40 to 125 -30 to +85 240oC, 10sec(Lead only)
Unit V V mW
o
C
oC oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 µs Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = -0.2mA IOL = 0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 VIN = VCC or 0V Chip Disabled tA= 30oC tA= 85oC, VCC = 1.8V ISB2 tA= 85oC, VCC = 2.0V tA= 85 C, VCC = 2.2V
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS.
o
Comments N16T1618
Min. 1.65 1.65 1.4 0.3 0.8VCCQ
Typ1 1.8
Max. 2.2 3.6 Vcc 0.4 0.2 0.5 0.5 4 25
Unit V V V V V V µA µA mA mA
I SB1 Standby Current3
tbd 40 70 100
µA µA µA µA
Stock No. 23183 - 04 4/03 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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