|Category||Memory => SRAM => Low Power => 1T-based Pseudo SRAMs|
|Title||1T-based Pseudo SRAMs|
|Description||32Mb, , 2Mb X 16, 1.65 - 1.95, 60, Page Mode, 48-BGA,|
|Company||NanoAmp Solutions, Inc.|
|Datasheet||Download N32T1618C1B datasheet
NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com
The is an integrated memory device containing a 32 Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2,097,152 words by 16 bits. It is designed to be compatible in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device includes a ZZ input for deep sleep as well as several other power saving modes: partial array refresh mode where data is retained in a portion of the array and temperature compensated refresh. Both these modes reduce standby current drain. The N32T1618C1B can be operated in a standard asynchronous mode and data can also be read a 4-word page mode for fast access times. The VFBGA package has separate power rails, VccQ and VssQ for the I/O to be run from a separate power supply from the device core.Features
Dual voltage rails for optimum power & performance Vcc to 1.95V VccQ 1.70V1.95V VccQ 2.3V2.7V VccQ 2.7V3.3V Fast Cycle Times TACC 60 nS TPACC < 15 nS Very low standby current ISB < 70µA Very low operating current Icc < 25mA PASR (Partial Array Self Refresh) TCR (Temperature Compensated Refresh) 48-Pin VFBGA, Wafers Available
Part Number N32T1618C1BZ Package Type 48 - BGA Operating Temperature to +85oC Power Supply - 1.95 Speed 60/70 ns Standby Operating Current (ISB), Current (Icc), Max @ 1MHz
Pin Function Address Inputs Write Enable Input Chip Enable Input Deep Sleep Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Ground Power I/O only Ground I/O only
Stock No. 23279 - Rev A 6/03 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.NanoAmp Solutions, Inc. Figure 2: Functional Block Diagram
Page Address Decode Logic Word Address Decode Logic
X X3 UB/LB ZZ I/O1 High Z High Z Data In Data Out High Z High-Z MODE Standby2 Active Write Read Active Set register Deep Sleep POWER Standby Active Standby4 Active Standby4 Active Deep Sleep
1. When UB and LB are in select mode (low), - I/O15 are affected as shown. When LB only is in the select mode only - IO7 are affected as shown. When is in the select mode only - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. 4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any external influence.
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 1 MHz, = 25oC VIN = 1 MHz, 25 C1. These parameters are verified in device characterization and are not 100% tested
NanoAmp Solutions, Inc. Table 5: Absolute Maximum Ratings1
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Voltage on VCCQ Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC VCCQ PD TSTG TA TSOLDER
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.Table 6: Operating Characteristics (Over Specified Temperature Range)
Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current 1 µs Cycle Time2 Read/Write Operating Supply Current 70 ns Cycle Time2 Standby Current3 VIN = VCC or 0V Chip Disabled VCC = VCCMAX Symbol VCC VCCQ = 1.8V VCCQ VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = -0.2mA IOL = 0.2mA VIN 0 to VCC OE = VIH or Chip Disabled VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 VIN = VCC or 0V Chip Disabled VCC = VCCMAX, tA= 85oC VCCQ = 2.5V VCCQ = 3.0V Comments Min. Typ1 1.8 Max. µA mA Unit V
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS.
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