Details, datasheet, quote on part number: N32T1618CBB
CategoryMemory => SRAM => Low Power => 1T-based Pseudo SRAMs
Title1T-based Pseudo SRAMs
Description32Mb, , 2Mb X 16, 1.65 - 1.95, 60/70, Burst Mode, 54-BGA,
CompanyNanoAmp Solutions, Inc.
DatasheetDownload N32T1618CBB datasheet


Features, Applications

NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877

32Mb Ultra-Low Power Async, Page and Burst CMOS PSRAM

The is an integrated memory device containing a 32 Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2,097,152 words by 16 bits. It is designed to be compatible in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device includes a deep power-down mode as well as several other power saving modes: Partial Array Self Refresh mode where data is retained in a portion of the array and Temperature Compensated Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode, a 16-word page mode and a highperformance burst mode. The device has separate power rails, VccQ and VssQ for the I/O to be run from a separate power supply from the device core.Ball Configuration 54-Ball BGA

Single Device Supports Asynchronous, Page and Burst Operations

Dual voltage rails for optimal performance VCC 1.70V1.95V VCCQ 1.70V2.25V VCCQ 2.3V2.7V (future) VCCQ 2.7V3.3V future)

Burst Mode Continuous Write Burst Burst Mode Read Access: 16 or Continuous
MAX clock rate: 104 MHz (tCLK = 9.62ns) Initial latency: 39ns (4 clocks) @ 104 MHz tACLK: @ 104 MHz

Sixteen-word page size Interpage read access: 70ns Intrapage read access: 20ns Low Power Consumption Asynchronous Read < 25mA Intrapage Read < 15mA Burst Read < 35mA Continuous Burst Read < 15mA Standby: 90A Deep power-down < 10A (MAX) Low Power Features Partial Array Self Refresh (PASR) Temperature Compensated Refresh (TCR) Deep Power-Down mode (DPD) High Performance access of 70ns and 85ns High frequency operation of 104M and 66MHz Temperature Range +85C 54-Ball VFBGA


Part Number N32T1628CBBZ N32T1638CBBZ BGA - 1.95 Package Operating Type Temperature Power Supply I/O Supply @ 1MHz Speed Standby Current (ISB), Max Operating Current (Icc), Max

This is an ADVANCE DATASHEET and subject to change without notice.

The a 32Mb device organized x 16 bits. These devices include the industry standard burst mode Flash interface that dramatically increases read/write bandwidth when compared with other low-power SRAM or PseudoSRAM offerings. To operate seamlessly on a burst Flash bus, a transparent self-refresh mechanism is incorporated. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The Bus Configuration Register (BCR) defines how the device interacts with the system memory bus and is nearly identical to its counterpart found on burst-mode Flash devices. The Refresh Configuration Register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up A[20-0] Address Decode Logic 2,048Kx 16 Refresh Configuration Register Bus Configuration Register CE# WE# OE# CLK ADV# CRE WAIT LB# UB# DRAM MEMORY ARRAY Input/ Output Mux and Buffers and can be updated any time during normal operation. Special attention has been focused on standby current consumption during self-refresh. The N32T1618CBB device includes three systemaccessible mechanisms used to minimize standby current. Partial Array Self Refresh (PASR) limits refresh to only that part of the DRAM array that contains essential data. Temperature Compensated Refresh (TCR) is used to adjust the refresh rate according to the ambient temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep Power Down (DPD) halts the refresh operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are adjusted through the Refresh Configuration Register.

Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the Bus Configuration Register or the Refresh Configuration Register. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising (or falling, depending upon the Bus Configuration Register setting) CLK edge when ADV# is active, or upon a rising ADV# edge, whichever occurs first. CLK is static during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. CLK must be held LOW during asynchronous or page mode transactions. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during READ and WRITE operations. ADV# may be driven LOW during asynchronous READ and WRITE operations. Control Register Enable: When CRE is HIGH, write operations load the Refresh Control Register or Bus Control Register. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a control register or to the memory array. Upper Byte Enable. DQ <8:15> Lower Byte Enable. DQ <0:7>

Input/Out- Data Inputs/Outputs put Output Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. Internally not connected Device Power Supply: [1.70V-1.95V] Power supply for device core operation. I/O Power Supply: 2.5V, 3.0V]Power supply for input/output buffers. All Vss supply pins must be connected to ground. All VssQ supply pins must be connected to ground.

NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT signal will be driven to an undefined state when operating in asynchronous or page mode. Otherwise, WAIT will be in High-Z condition.


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